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70P248L55BYI PDF预览

70P248L55BYI

更新时间: 2024-11-11 14:40:07
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
23页 168K
描述
Dual-Port SRAM, 4KX16, 55ns, CMOS, PBGA100, 6 X 6 MM, 1 MM HEIGHT, 0.50 MM PITCH, BGA-100

70P248L55BYI 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:BGA包装说明:6 X 6 MM, 1 MM HEIGHT, 0.50 MM PITCH, BGA-100
针数:100Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.45Is Samacsys:N
最长访问时间:55 nsI/O 类型:COMMON
JESD-30 代码:S-PBGA-B100JESD-609代码:e0
长度:6 mm内存密度:65536 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端口数量:2端子数量:100
字数:4096 words字数代码:4000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:4KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装等效代码:BGA100,10X10,20
封装形状:SQUARE封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:1.8,2.5/3 V认证状态:Not Qualified
座面最大高度:1 mm最大待机电流:0.000008 A
最小待机电流:1.7 V子类别:SRAMs
最大压摆率:0.025 mA最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn63Pb37)
端子形式:BALL端子节距:0.5 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:20
宽度:6 mmBase Number Matches:1

70P248L55BYI 数据手册

 浏览型号70P248L55BYI的Datasheet PDF文件第2页浏览型号70P248L55BYI的Datasheet PDF文件第3页浏览型号70P248L55BYI的Datasheet PDF文件第4页浏览型号70P248L55BYI的Datasheet PDF文件第5页浏览型号70P248L55BYI的Datasheet PDF文件第6页浏览型号70P248L55BYI的Datasheet PDF文件第7页 
VERY LOW POWER 1.8V  
8K/4K x 16 DUAL-PORT  
STATIC RAM  
IDT70P258/248L  
Š
Features  
Left port is selectable 3.0V or 2.5V I/O  
Right port is 1.8V I/O  
M/S = VSS for BUSY input on Slave  
Input Read Register  
Output Drive Register  
BUSY and Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
LVTTL-compatible, single 1.8V (±100mV) power supply  
Available in 100 Ball 0.5mm-pitch BGA  
Industrial temperature range (-40°C to +85°C)  
Green parts available, see ordering information  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
Industrial:55ns (max.)  
Low-power operation  
IDT70P258/248L  
Active:27mW(typ.)  
Standby:3.6µW(typ.)  
Separate upper-byte and lower-byte control for multiplexed  
bus compatibility  
IDT70P258/248 easily expands data bus width to 32 bits or  
more using the Master/Slave select when cascading more  
than one device  
M/S = VDD for BUSY output flag on Master  
Functional Block Diagram  
R/W  
R
R/W  
L
UBR  
UBL  
LB  
CE  
OE  
R
LBL  
CEL  
OEL  
R
R
,
I/O8L-I/O15L  
I/O0L-I/O7L  
I/O8R-I/O15R  
I/O  
Control  
I/O  
Control  
I/O0R-I/O7R  
BUSY (2,3)  
L
(2,3)  
BUSY  
R
(1)  
12R  
(1)  
A
A
12L  
Address  
Decoder  
Address  
Decoder  
MEMORY  
ARRAY  
A0R  
A
0L  
CE  
L
CE  
OE  
R/W  
ODR  
R
INPUT  
READ REGISTER  
AND  
OE  
L
L
R
R/W  
R
OUTPUT  
DRIVE REGISTER  
ODR  
0
-
4
IRR0,IRR1  
SFEN  
13  
13  
CE  
OE  
R/W  
L
CE  
R
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
L
OE  
R
L
R/W  
R
SEM  
INTR  
R
(3)  
SEM  
L
(3)  
M/S  
INTL  
5675 drw 01  
NOTES:  
1. A12X is a NC for IDT70P248.  
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
3. BUSY outputs and INT outputs are non-tri-stated push-pull.  
JANUARY 2009  
1
DSC-5675/8  
©2009IntegratedDeviceTechnology,Inc.  

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