Datasheet > 70P256L55BYI8

70P256L55BYI8

更新时间： 2024-11-12 04:20:55

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
23页	166K
描述
SRAM

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中文翻译

获取价格

数据手册

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70P256L55BYI8 数据手册

PRELIMINARY

IDT70P256/246L

VERY LOW POWER 1.8V

8K/4K x 16 DUAL-PORT

STATIC RAM

Features

◆

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

Input Read Register

◆

Output Drive Register

BUSY and Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

◆

– Industrial:55ns (max.)

Low-power operation

IDT70P256/246L

◆

Active:27mW(typ.)

Standby:3.6µW(typ.)

Separate upper-byte and lower-byte control for multiplexed

bus compatibility

Supports 3.0V and 2.5V I/O's

Fully asynchronous operation from either port

LVTTL-compatible, single 1.8V (±100mV) power supply

Available in 100 Ball 0.5mm-pitch BGA

Industrial temperature range (-40°C to +85°C)

Green parts available, see ordering information

◆

Functional Block Diagram

R/W

I/O8L-I/O15L

I/O0L-I/O7L

I/O8R-I/O15R

I/O

Control

I/O

Control

I/O0R-I/O7R

BUSY ⁽²⁾

(2)

BUSY

(1)

12R

12L

Address

Decoder

Address

Decoder

MEMORY

ARRAY

R/W

IRR

R/W

ODR

INPUT

READ REGISTER

AND

OUTPUT

DRIVE REGISTER

ODR

0,IRR1

SFEN

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

(2)

INT ⁽²⁾

INT

5699 drw 01

NOTES:

1. A12X is a NC for IDT70P246.

2. BUSY outputs and INT outputs are non-tri-stated push-pull.

JULY 2008

DSC-5699/1

12 3 4 5 6 7...23

中文翻译

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