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70P265L90BYGI PDF预览

70P265L90BYGI

更新时间: 2024-11-06 15:29:03
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
22页 156K
描述
Dual-Port SRAM, 16KX16, 90ns, CMOS, PBGA100, 0.5 MM PITCH, GREEN, BGA-100

70P265L90BYGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:BGA, BGA100,10X10,20针数:100
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.52
最长访问时间:90 ns其他特性:IT CAN OPERATE ALSO 2.5 TO 3 VOLT
I/O 类型:COMMONJESD-30 代码:S-PBGA-B100
JESD-609代码:e1内存密度:262144 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端口数量:2端子数量:100
字数:16384 words字数代码:16000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:16KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA100,10X10,20
封装形状:SQUARE封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:1.8/3 V认证状态:Not Qualified
最大待机电流:0.000008 A子类别:SRAMs
最大压摆率:0.06 mA最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:0.5 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
Base Number Matches:1

70P265L90BYGI 数据手册

 浏览型号70P265L90BYGI的Datasheet PDF文件第2页浏览型号70P265L90BYGI的Datasheet PDF文件第3页浏览型号70P265L90BYGI的Datasheet PDF文件第4页浏览型号70P265L90BYGI的Datasheet PDF文件第5页浏览型号70P265L90BYGI的Datasheet PDF文件第6页浏览型号70P265L90BYGI的Datasheet PDF文件第7页 
IDT70P265/255/245L  
VERY LOW POWER 1.8V  
16K/8K/4K X 16 DUAL-PORT  
STATIC RAM  
Š
Features  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
One port with dedicated time-muliplexed address/data  
(ADM) interface  
Power supply isolation functionality to aid system power  
management  
Separate upper-byte and lower-byte control  
Supports 3.0V, 2.5V and 1.8V I/O's  
Input Read Register  
Output Drive Register  
BUSY and Interrupt Flag  
On-chip port arbitration logic  
Fully asynchronous operation from either port  
Available in 100 Ball 0.5mm-pitch BGA  
Industrial temperature range (-40°C to +85°C)  
Green parts available, see ordering information  
One port configurable to standard SRAM or time-multi-  
plexed address/data interface  
High-speed access  
Industrial: 65ns (max.), ADM mode  
Industrial: 40ns (max.), Standard SRAM mode  
Low-power operation  
IDT70P265/255/245L  
Active:27mW(typ.)  
Standby:3.6µW(typ.)  
Functional Block Diagram  
IRR1 – IRR0 (2)  
ODR4 – ODR0  
SFEN  
IRR/ODR  
I/O15L – I/O8L  
Data <15..0>  
I/O7L – I/O0L  
I/O15R – I/O8R  
Data <15..0>  
I/O7R – I/O0R  
Mux’ed  
Mux’ed  
Address /  
Memory Array  
Address /  
Data  
I/O Control  
16K/8K/4K x 16  
Data  
I/O Control  
ADVL  
ADVR  
UBR  
LBR  
AddrL <13..0>  
AddrR <13..0>  
UBL  
LBL  
A13R – A0R  
Address  
Decode  
Address  
Decode  
MSEL  
CSL  
OEL  
CSR  
Control Logic  
OER  
WEL  
WER  
BUSYR  
INTR  
BUSYL  
INTL  
7145 drw 01  
NOTES:  
1. A13 - A0 for IDT70P265; A12 - A0 for IDT70P255; A11 - A0 for IDT70P245.  
2. IRR0 and IRR1 are not available for IDT70P265.  
SEPTEMBER 2011  
1
DSC-7145/3  
©2011IntegratedDeviceTechnology,Inc.  

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