Datasheet > 70P27S12PFI8

70P27S12PFI8

更新时间： 2023-02-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
19页	157K
描述
TQFP-100, Reel

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数据手册

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70P27S12PFI8 数据手册

HIGH-SPEED 1.8V

32K x 16

ASYNCHRONOUS

DUAL-PORT

IDT70P27L

STATIC RAM

Features:

◆

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

LVTTL-compatible, single 1.8V (1.7V < VDD < 1.95V) power

supply

Available in 100-pin Thin Quad Flatpack (TQFP)

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

◆

– Commercial:12/15ns (max.)

– Industrial:15ns (max.)

Low-power operation

◆

– IDT70P27L

Active:306mW(typ.)

Standby:360µW(typ.)

Separate upper-byte and lower-byte control for bus

matching capability

Dual chip enables allow for depth expansion without

external logic

IDT70P27 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

◆

Green parts available, see ordering information

FunctionalBlockDiagram

R/W

R/WR

CE0L

CE0R

CE1L

CE1R

I/O8-15L

I/O0-7L

I/O8-15R

I/O0-7R

I/O

Control

I/O

Control

(1,2)

BUSY

32Kx16

14R

14L

Address

Decoder

Address

Decoder

MEMORY

ARRAY

70P27

14L

CE0R

14R

CE0L

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE1L

CE1R

R/WR

SEM

INT

SEM

(2)

INT

M/S⁽²⁾

NOTES:

5694 drw 01

1) BUSY is an input as a Slave (M/S=V^IL) and an output as a Master (M/S=VIH).

2) BUSY and INT are non-tri-state totem-pole outputs (push-pull).

JANUARY 2009

6.01

DSC 5694/2

12 3 4 5 6 7...19

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