Datasheet > 70P3307S166RM

70P3307S166RM

更新时间： 2024-11-09 19:03:35

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器内存集成电路
页数	文件大小	规格书
20页	617K
描述
FCBGA-576, Tray

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技术参数
数据手册

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70P3307S166RM 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	FCBGA
针数：	576	Reach Compliance Code：	not_compliant
风险等级：	5.84	JESD-609代码：	e1
内存集成电路类型：	QDR SRAM	湿度敏感等级：	4
峰值回流温度（摄氏度）：	245	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

70P3307S166RM 数据手册

PRELIMINARY DATASHEET

IDT70P3307

1024K/512K x18

SYNCHRONOUS

DUAL QDR-II

IDT70P3337

Features

– Four word transfers per clock cycle per port (four word bursts

on 2 ports)

◆

18Mb Density (1024K x 18)

◆

Port Enable pins (E0,E1) for depth expansion

Dual Echo Clock Output with DLL-based phase alignment

High Speed Transceiver Logic inputs that can be scaled to

receive signals from 1.4V to 1.9V

– Also available 9Mb Density (512K x 18)

QDR-II x 18 Burst-of-2 Interface

– Commercial: 233MHz, 250MHz

◆

Separate, Independent Read and Write Data Ports

– Supports concurrent transactions

◆

Scalable output drivers

– Drives HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V

– Output impedance adjustable from 35 ohms to 70 ohms

1.8V Core Voltage (VDD)

◆

Dual Echo Clock Output

Two-Word Burst on all DPRAM accesses

DDR (Double Data Rate) Multiplexed Address Bus

– One Read and One Write request per clock cycle

DDR (Double Data Rate) Data Buses

– Four word burst data (Two Read and Two Write) per clock on

each port

◆

576-ball Flip Chip BGA (25mm x 25mm, 1.0mm ball pitch)

JTAG Interface - IEEE 1149.1 Compliant

◆

Functional Block Diagram

VREFL

VREFR

P[1:0]

ER[1:0]

EL[1:0]

LEFT PORT

DATA

RIGHT PORT

DATA

AND LOGIC

0L- D17L

0R-

D17R

WRITE DRIVER

(1)

0L-

17L

0R- Q17R

1024/512K x 18

MEMORY

ARRAY

CQL, CQL

CQR, CQR

(2)

18R

(2)

0R-

A0L-

18L

, C

^ORK

, K

^ORK

, K

LEFT PORT

ADDRESS

AND LOGIC

RIGHT PORT

ADDRESS

AND LOGIC

ADDRESS DECODE

BW0R- BW1R

BW0L- BW1L

TCK

TMS

TRST

TDI

6725 drw01

JTAG

VREFR

VREFL

TDO

NOTES:

1. Input pin to adjust the device outputs to the system data bus impedance.

2. Address A18 is a INC for IDT70P3337. Disabled input pin (Diode tied to VDD and VSS).

January 29, 2009

©2008 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice. NOT AN OFFER FOR SALE The information

presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale

or an o

or sale that creates a contractual po

r of acceptance.

QDR

nd Quad

ta Rate R

ompri

e a new

ily of products developed by Cypress Semicondor, ID

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DSC-6725/1

12 3 4 5 6 7...20

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与70P3307S166RM相关器件

型号	品牌	获取价格	描述	数据表
70P3307S166RMI	IDT	获取价格	FCBGA-576, Tray
70P3307S167RM	IDT	获取价格	FCBGA-576, Tray
70P3307S167RMI	IDT	获取价格	FCBGA-576, Tray
70P3307S200RM	IDT	获取价格	FCBGA-576, Tray
70P3307S200RMI	IDT	获取价格	FCBGA-576, Tray
70P3307S233RM	IDT	获取价格	FCBGA-576, Tray
70P3307S233RMI	IDT	获取价格	FCBGA-576, Tray
70P3307S250RM	IDT	获取价格	FCBGA-576, Tray
70P3337S166RM	IDT	获取价格	FCBGA-576, Tray
70P3337S166RMI	IDT	获取价格	FCBGA-576, Tray

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