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70P27L25PFI8 PDF预览

70P27L25PFI8

更新时间: 2024-02-21 04:15:04
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
19页 157K
描述
TQFP-100, Reel

70P27L25PFI8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:,针数:100
Reach Compliance Code:not_compliant风险等级:5.59
JESD-609代码:e0内存集成电路类型:DUAL-PORT SRAM
湿度敏感等级:3峰值回流温度(摄氏度):240
端子面层:Tin/Lead (Sn/Pb)处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

70P27L25PFI8 数据手册

 浏览型号70P27L25PFI8的Datasheet PDF文件第2页浏览型号70P27L25PFI8的Datasheet PDF文件第3页浏览型号70P27L25PFI8的Datasheet PDF文件第4页浏览型号70P27L25PFI8的Datasheet PDF文件第5页浏览型号70P27L25PFI8的Datasheet PDF文件第6页浏览型号70P27L25PFI8的Datasheet PDF文件第7页 
HIGH-SPEED 1.8V  
32K x 16  
ASYNCHRONOUS  
DUAL-PORT  
IDT70P27L  
Š
STATIC RAM  
Features:  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Busy and Interrupt Flags  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
LVTTL-compatible, single 1.8V (1.7V < VDD < 1.95V) power  
supply  
Available in 100-pin Thin Quad Flatpack (TQFP)  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
– Commercial:12/15ns (max.)  
Industrial:15ns (max.)  
Low-power operation  
IDT70P27L  
Active:306mW(typ.)  
Standby:360µW(typ.)  
Separate upper-byte and lower-byte control for bus  
matching capability  
Dual chip enables allow for depth expansion without  
external logic  
IDT70P27 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
Green parts available, see ordering information  
FunctionalBlockDiagram  
R/W  
L
R/WR  
UB  
L
UB  
R
CE0L  
CE0R  
CE1L  
CE1R  
OE  
R
OE  
L
L
LB  
R
LB  
I/O8-15L  
I/O0-7L  
I/O8-15R  
I/O0-7R  
I/O  
Control  
I/O  
Control  
,
(1,2)  
(1,2)  
BUSY  
L
BUSY  
R
32Kx16  
A
14R  
0R  
A
14L  
0L  
Address  
Decoder  
Address  
Decoder  
MEMORY  
ARRAY  
70P27  
A
A
A
14L  
A
A
CE0R  
14R  
0R  
A
CE0L  
0L  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE1L  
CE1R  
OE  
OE  
L
R
R/  
WL  
R/WR  
L
L
SEM  
INT  
SEM  
R
(2)  
(2)  
INT  
R
M/S(2)  
NOTES:  
5694 drw 01  
1) BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).  
2) BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
JANUARY 2009  
6.01  
1
DSC 5694/2  
©2009IntegratedDeviceTechnology,Inc.  

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