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70P27L12PFG PDF预览

70P27L12PFG

更新时间: 2024-02-05 21:08:09
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
19页 157K
描述
TQFP-100, Tray

70P27L12PFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:14 X 14 MM, 1.60 MM HEIGHT, 0.50 MM PITCH, GREEN, TQFP-100针数:100
Reach Compliance Code:unknownECCN代码:3A991
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:12 nsI/O 类型:COMMON
JESD-30 代码:R-PQFP-G100JESD-609代码:e3
长度:14 mm内存密度:524288 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端口数量:2端子数量:100
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP100,.63SQ,20
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:1.8 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.005 A
最小待机电流:1.7 V子类别:SRAMs
最大压摆率:0.23 mA最大供电电压 (Vsup):1.95 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

70P27L12PFG 数据手册

 浏览型号70P27L12PFG的Datasheet PDF文件第2页浏览型号70P27L12PFG的Datasheet PDF文件第3页浏览型号70P27L12PFG的Datasheet PDF文件第4页浏览型号70P27L12PFG的Datasheet PDF文件第5页浏览型号70P27L12PFG的Datasheet PDF文件第6页浏览型号70P27L12PFG的Datasheet PDF文件第7页 
HIGH-SPEED 1.8V  
32K x 16  
ASYNCHRONOUS  
DUAL-PORT  
IDT70P27L  
Š
STATIC RAM  
Features:  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Busy and Interrupt Flags  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
LVTTL-compatible, single 1.8V (1.7V < VDD < 1.95V) power  
supply  
Available in 100-pin Thin Quad Flatpack (TQFP)  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
– Commercial:12/15ns (max.)  
Industrial:15ns (max.)  
Low-power operation  
IDT70P27L  
Active:306mW(typ.)  
Standby:360µW(typ.)  
Separate upper-byte and lower-byte control for bus  
matching capability  
Dual chip enables allow for depth expansion without  
external logic  
IDT70P27 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
Green parts available, see ordering information  
FunctionalBlockDiagram  
R/W  
L
R/WR  
UB  
L
UB  
R
CE0L  
CE0R  
CE1L  
CE1R  
OE  
R
OE  
L
L
LB  
R
LB  
I/O8-15L  
I/O0-7L  
I/O8-15R  
I/O0-7R  
I/O  
Control  
I/O  
Control  
,
(1,2)  
(1,2)  
BUSY  
L
BUSY  
R
32Kx16  
A
14R  
0R  
A
14L  
0L  
Address  
Decoder  
Address  
Decoder  
MEMORY  
ARRAY  
70P27  
A
A
A
14L  
A
A
CE0R  
14R  
0R  
A
CE0L  
0L  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE1L  
CE1R  
OE  
OE  
L
R
R/  
WL  
R/WR  
L
L
SEM  
INT  
SEM  
R
(2)  
(2)  
INT  
R
M/S(2)  
NOTES:  
5694 drw 01  
1) BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).  
2) BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
JANUARY 2009  
6.01  
1
DSC 5694/2  
©2009IntegratedDeviceTechnology,Inc.  

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