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70P249L90BYI PDF预览

70P249L90BYI

更新时间: 2024-11-11 18:49:43
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
22页 146K
描述
Application Specific SRAM, 4KX16, 90ns, CMOS, PBGA100, 0.50 MM, BGA-100

70P249L90BYI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active包装说明:BGA, BGA100,10X10,20
Reach Compliance Code:not_compliant风险等级:5.69
最长访问时间:90 ns其他特性:IT ALSO OPERATES AT SUPPLY VOLTAGE 2.5 V AND 3 V NOMINAL
I/O 类型:COMMONJESD-30 代码:S-PBGA-B100
JESD-609代码:e0内存密度:65536 bit
内存集成电路类型:APPLICATION SPECIFIC SRAM内存宽度:16
功能数量:1端口数量:2
端子数量:100字数:4096 words
字数代码:4000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:4KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA100,10X10,20封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:1.8/3 V
认证状态:Not Qualified最大待机电流:0.000006 A
子类别:SRAMs最大压摆率:0.06 mA
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30Base Number Matches:1

70P249L90BYI 数据手册

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IDT70P269/259/249L  
VERY LOW POWER 1.8V  
16K/8K/4K X 16 DUAL-PORT  
STATIC RAM  
Š
Features  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
Both ports configurable to standard SRAM or time-  
multiplexed address/data interface  
High-speed access  
Power supply isolation functionality to aid system power  
management  
Separate upper-byte and lower-byte control  
Input Read Register  
Output Drive Register  
BUSY and Interrupt Flag  
Industrial: 65ns (max.), ADM mode  
Industrial: 40ns (max.), Standard SRAM mode  
Low-power operation  
On-chip port arbitration logic  
Fully asynchronous operation from either port  
Available in 100 Ball 0.5mm-pitch BGA  
Industrial temperature range (-40°C to +85°C)  
Green parts available, see ordering information  
IDT70P269/259/249L  
Active:27mW(typ.)  
Standby:3.6µW(typ.)  
Supports 3.0V, 2.5V and 1.8V I/O's  
Functional Block Diagram  
IRR1 – IRR0 (2)  
ODR4 – ODR0  
SFEN#  
IRR/ODR  
I/O15L – I/O8L  
Data <15..0>  
I/O7L – I/O0L  
I/O15R – I/O8R  
Data <15..0>  
I/O7R – I/O0R  
Mux’ed  
Mux’ed  
Address /  
Memory Array  
Address /  
Data  
I/O Control  
16K/8K/4K x 16  
Data  
I/O Control  
ADVL  
ADVR  
UBR  
LBR  
AddrR <13..0>  
AddrR <13..0>  
UBL  
LBL  
A13L – A0L  
A13R – A0R  
Address  
Decode  
Address  
Decode  
MSELL  
MSELR  
CSL  
OEL  
CSR  
Control Logic  
OER  
WEL  
WER  
BUSYR  
INTR  
BUSYL  
INTL  
7146 drw 01  
NOTES:  
1. A13 - A0 for IDT70P269; A12 - A0 for IDT70P259; A11 - A0 for IDT70P249.  
2. IRR0 and IRR1 are not available for IDT70P269.  
OCTOBER 2008  
1
DSC-7146/1  
©2008IntegratedDeviceTechnology,Inc.  

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