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70P247L55BYGI PDF预览

70P247L55BYGI

更新时间: 2024-02-10 05:48:45
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
23页 163K
描述
Dual-Port SRAM, 4KX16, 55ns, CMOS, PBGA100, 6 X 6 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, BGA-100

70P247L55BYGI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:6 X 6 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, BGA-100
针数:100Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.49最长访问时间:55 ns
I/O 类型:COMMONJESD-30 代码:S-PBGA-B100
JESD-609代码:e1长度:6 mm
内存密度:65536 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:16湿度敏感等级:3
功能数量:1端口数量:2
端子数量:100字数:4096 words
字数代码:4000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:4KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:VFBGA
封装等效代码:BGA100,10X10,20封装形状:SQUARE
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:1.8 V
认证状态:Not Qualified座面最大高度:1 mm
最大待机电流:0.000008 A最小待机电流:1.7 V
子类别:SRAMs最大压摆率:0.025 mA
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:6 mm
Base Number Matches:1

70P247L55BYGI 数据手册

 浏览型号70P247L55BYGI的Datasheet PDF文件第2页浏览型号70P247L55BYGI的Datasheet PDF文件第3页浏览型号70P247L55BYGI的Datasheet PDF文件第4页浏览型号70P247L55BYGI的Datasheet PDF文件第5页浏览型号70P247L55BYGI的Datasheet PDF文件第6页浏览型号70P247L55BYGI的Datasheet PDF文件第7页 
VERY LOW POWER 1.8V  
8K/4K x 16 DUAL-PORT  
STATIC RAM  
IDT70P257/247L  
Features  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
M/S = VDD for BUSY output flag on Master  
M/S = VSS for BUSY input on Slave  
Input Read Register  
Output Drive Register  
BUSY and Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
LVTTL-compatible, single 1.8V (±100mV) power supply  
Available in 100 Ball 0.5mm-pitch BGA  
Industrial temperature range (-40°C to +85°C)  
Green parts available, see ordering information  
Industrial:55ns (max.)  
Low-power operation  
IDT70P257/247L  
Active:27mW(typ.)  
Standby:3.6µW(typ.)  
Separate upper-byte and lower-byte control for multiplexed  
bus compatibility  
IDT70P257/247 easily expands data bus width to 32 bits or  
more using the Master/Slave select when cascading more  
than one device  
Functional Block Diagram  
R/W  
R
R/W  
L
UBR  
UBL  
LB  
CE  
OE  
R
LBL  
CEL  
OEL  
R
R
,
I/O8L-I/O15L  
I/O0L-I/O7L  
I/O8R-I/O15R  
I/O  
Control  
I/O  
Control  
I/O0R-I/O7R  
BUSY (2,3)  
L
(2,3)  
BUSY  
R
(1)  
12R  
(1)  
A
A
12L  
Address  
Decoder  
Address  
Decoder  
MEMORY  
ARRAY  
A0R  
A
0L  
CE  
L
CE  
OE  
R/W  
ODR  
R
INPUT  
READ REGISTER  
AND  
OE  
L
L
R
R/W  
R
OUTPUT  
DRIVE REGISTER  
ODR  
0
-
4
IRR0,IRR1  
SFEN  
13  
13  
CE  
OE  
R/W  
L
CE  
R
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
L
OE  
R
L
R/W  
R
SEM  
INTR  
R
(3)  
SEM  
L
(3)  
M/S  
INTL  
5684 drw 01  
NOTES:  
1. A12X is a NC for IDT70P247.  
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
3. BUSY outputs and INT outputs are non-tri-stated push-pull.  
JANUARY 2009  
1
DSC-5684/4  
©2009IntegratedDeviceTechnology,Inc.  

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