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5T9304I PDF预览

5T9304I

更新时间: 2024-09-22 01:22:51
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
17页 153K
描述
LVDS, 1:4 Clock Buffer Terabuffer

5T9304I 数据手册

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LVDS, 1:4 Clock Buffer Terabuffer™  
5T9304I  
DATA SHEET  
General Description  
Features  
The 5T9304I differential clock buffer is a user-selectable differential  
input to four LVDS outputs. The fanout from a differential input to four  
LVDS outputs reduces loading on the preceding driver and provides  
an efficient clock distribution network. The 5T9304I can act as a  
translator from a differential HSTL, eHSTL, LVEPECL (2.5V),  
LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A  
single-ended 3.3V / 2.5V LVTTL input can also be used to translate  
to LVDS outputs. The redundant input capability allows for an  
asynchronous change-over from a primary clock source to a  
secondary clock source. Selectable reference inputs are controlled  
by SEL.  
Guaranteed low skew: 50ps (maximum)  
Very low duty cycle distortion: 125ps (maximum)  
Propagation delay: 1.9ns (maximum)  
Up to 450MHz operation  
Selectable inputs  
Hot insertable and over-voltage tolerant inputs  
3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V),  
LVPECL (3.3V), CML or LVDS input interface  
Selectable differential inputs to four LVDS outputs  
2.5V VDD  
-40°C to 85°C ambient operating temperature  
Available in lead-free (RoHS 6) package  
The 5T9304I outputs can be asynchronously enabled/disabled.  
When disabled, the outputs will drive to the value selected by the GL  
pin. Multiple power and grounds reduce noise.  
Applications  
Clock distribution  
Pin Assignment  
A2  
A2  
GND  
PD  
1
2
24  
23  
GND  
VDD  
RESERVED  
VDD  
3
4
22  
21  
5
6
7
8
20  
19  
18  
17  
Q3  
Q3  
Q4  
Q1  
Q1  
Q2  
Q4  
Q2  
VDD  
SEL  
G
VDD  
GL  
A1  
9
16  
15  
14  
13  
10  
11  
12  
GND  
A1  
5T9304I  
24-Lead TSSOP, E-Pad  
4.40mm x 7.8mm x 0.925mm  
G Package  
Top View  
5T9304I Rev A 5/13/15  
1
©2015 Integrated Device Technology, Inc.  

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