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5T93GL16NLGI PDF预览

5T93GL16NLGI

更新时间: 2024-11-02 20:56:39
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
15页 187K
描述
VFQFPN-52, Tray

5T93GL16NLGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:VFQFPN
包装说明:HVQCCN, LCC52,.31SQ,20针数:52
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
系列:5T输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQCC-N52JESD-609代码:e3
长度:8 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:52
实输出次数:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC52,.31SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:2.5 V
Prop。Delay @ Nom-Sup:2 ns传播延迟(tpd):2 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.025 ns
座面最大高度:1 mm子类别:Clock Driver
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:8 mm最小 fmax:650 MHz
Base Number Matches:1

5T93GL16NLGI 数据手册

 浏览型号5T93GL16NLGI的Datasheet PDF文件第2页浏览型号5T93GL16NLGI的Datasheet PDF文件第3页浏览型号5T93GL16NLGI的Datasheet PDF文件第4页浏览型号5T93GL16NLGI的Datasheet PDF文件第5页浏览型号5T93GL16NLGI的Datasheet PDF文件第6页浏览型号5T93GL16NLGI的Datasheet PDF文件第7页 
2.5V LVDS 1:16  
IDT5T93GL16  
GLITCHLESS CLOCK BUFFER  
TERABUFFER™ II  
DESCRIPTION:  
FEATURES:  
TheIDT5T93GL162.5Vdifferentialclockbufferisauser-selectablediffer-  
• Guaranteed Low Skew < 25ps (max)  
• Very low duty cycle distortion < 100ps (max)  
• High speed propagation delay < 2ns (max)  
• Up to 650MHz operation  
entialinputtosixteenLVDSoutputs. Thefanoutfromadifferentialinputtosixteen  
LVDSoutputsreducesloadingontheprecedingdriverandprovidesanefficient  
clockdistributionnetwork. TheIDT5T93GL16canactasatranslatorfroma  
differentialHSTL,eHSTL,LVEPECL (2.5V),LVPECL(3.3V),CML,orLVDS  
input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be  
usedtotranslatetoLVDSoutputs. Theredundantinputcapabilityallowsfora  
glitchless change-over from a primary clock source to a secondary clock  
source. SelectableinputsarecontrolledbySEL. Duringtheswitchover, the  
outputwilldisablelowforuptothreeclockcyclesofthepreviously-selectedinput  
clock. The outputs will remain low for up to three clock cycles of the newly-  
selectedclock,afterwhichtheoutputswillstartfromthenewly-selectedinput.  
AFSELpinhasbeenimplementedtocontroltheswitchoverincaseswherea  
clocksourceisabsentorisdriventoDClevelsbelowtheminimumspecifications.  
The IDT5T93GL16 outputs can be asynchronously enabled/disabled.  
Whendisabled,theoutputswilldrivetothevalueselectedbytheGLpin. Multiple  
power and grounds reduce noise.  
• Glitchless input clock switching  
• Selectable inputs  
• Hot insertable and over-voltage tolerant inputs  
• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),  
CML, or LVDS input interface  
• Selectable differential inputs to sixteen LVDS outputs  
• Power-down mode  
• 2.5V VDD  
• Available in VFQFPN package  
APPLICATIONS:  
• Clock distribution  
FUNCTIONALBLOCKDIAGRAM  
GL  
G1  
Q1  
OUTPUT  
CONTROL  
Q1  
Q2  
OUTPUT  
CONTROL  
Q2  
Q3  
OUTPUT  
CONTROL  
PD  
Q3  
Q4  
Q4  
OUTPUT  
CONTROL  
Q5  
Q5  
OUTPUT  
CONTROL  
A1  
A1  
1
0
Q6  
Q6  
OUTPUT  
CONTROL  
A2  
A2  
Q7  
Q7  
OUTPUT  
CONTROL  
SEL  
Q8  
Q8  
OUTPUT  
CONTROL  
FSEL  
G2  
Q9  
Q9  
OUTPUT  
CONTROL  
Q10  
Q10  
OUTPUT  
CONTROL  
Q11  
Q11  
OUTPUT  
CONTROL  
Q12  
Q12  
OUTPUT  
CONTROL  
Q13  
Q13  
OUTPUT  
CONTROL  
Q14  
Q14  
OUTPUT  
CONTROL  
Q15  
Q15  
OUTPUT  
CONTROL  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
Q16  
Q16  
OUTPUT  
CONTROL  
INDUSTRIAL TEMPERATURE RAN
JANUARY 2007  
1
© 2007 Integrated Device Technology, Inc.  
DSC 6185/19  

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