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5T940-10NLI8 PDF预览

5T940-10NLI8

更新时间: 2024-11-02 20:06:47
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
11页 160K
描述
Clock Driver, PQCC28

5T940-10NLI8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.92
JESD-30 代码:S-PQCC-N28JESD-609代码:e0
湿度敏感等级:1端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCN
封装等效代码:LCC28,.24SQ,25封装形状:SQUARE
封装形式:CHIP CARRIER电源:2.5/3.3 V
认证状态:Not Qualified子类别:Clock Drivers
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:NO LEAD
端子节距:0.635 mm端子位置:QUAD
Base Number Matches:1

5T940-10NLI8 数据手册

 浏览型号5T940-10NLI8的Datasheet PDF文件第2页浏览型号5T940-10NLI8的Datasheet PDF文件第3页浏览型号5T940-10NLI8的Datasheet PDF文件第4页浏览型号5T940-10NLI8的Datasheet PDF文件第5页浏览型号5T940-10NLI8的Datasheet PDF文件第6页浏览型号5T940-10NLI8的Datasheet PDF文件第7页 
IDT5T940  
PRECISION CLOCK GENERATOR  
OC-192 APPLICATIONS  
FEATURES:  
DESCRIPTION:  
Input frequency:  
The IDT5T940 generates a high precision FEC (Forward Error Cor-  
rection) or non-FEC source clock for SONET/SDH systems as well as a  
source clock for Gigabit Ethernet systems. This device also has clock  
regeneration capability: it creates a "clean" version of the clock input by  
using the internal oscillator to square the input clock's rising and falling  
edges and remove jitter. In the event that the main clock input fails, the  
device automatically locks to a backup reference clock using a hitless  
switchover mechanism.  
- ForSONETnon-FEC:19.44MHz,38.88MHz,77.76MHz,155.52MHz,  
311.04MHz, or 622.08MHz  
- For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz,  
333.26MHz, or 666.52MHz  
- For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz,  
312.5MHz, or 625MHz  
- For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz,  
322.26MHz, or 644.53MHz  
• 3-levelinputs forfeedbackdivide ratioandoutputfrequencyrange  
selection  
• 1x, 2x, 4x, 8x, 16x, and 32x outputs on QOUT  
• Regenerated input clock or QOUT/4 on QREG  
Lock indicator  
This device detects loss ofvalidCLKINandleaves the VCOofthe PLLat  
thelastvalidfrequencywhileanalternateinputREFINis selected. IfCLKIN  
andREFINaredifferentfrequencies,themultiplicationfactorwillbeadjustedto  
retainthesameoutputfrequency.  
TheIDT5T940canactasatranslatorfromadifferentialLVPECL,LVDS,or  
single-ended LVTTL input to LVPECL or LVDS outputs. The IDT5T940-10  
has LVDSoutputs andthe IDT5T940-30has LVPECLoutputs.  
ThethreemodesofoutputfrequencyrangearecontrolledbytheSELmode,  
whichisa3-levelpin. WhenSELmodeishighorlow,theQOUT isamultiplied  
versionoftheinputclockwhileQREGisaregeneratedversionoftheinputclock.  
WhenSELmodeismid,theQOUTisamultipliedversionoftheinputclockwhile  
QREG isQOUT/4.  
• Power-down mode  
LVPECL or LVDS outputs  
Three modes of output frequency range  
- Mode0:QOUT range155.5-166.6MHz. QREG isaregeneratedversion  
ofthe inputclock.  
- Mode 1: QOUT range 622 - 666.5MHz. QREG output 155.5-166.6MHz.  
- Mode 2: QOUT range 622 - 666.5MHz. QREG is a regenerated version  
ofthe inputclockfrequency.  
TheIDT5T940featuresaselectableloopbandwidth.  
• Selectable loop bandwidths  
Hitless switchover  
Differential LVPECL, LVDS, or single-ended LVTTL input interface  
• 2.375 - 3.465V core and I/O  
APPLICATIONS:  
Terabit routers  
• Gigabit ethernet systems  
• SONET / SDH systems  
Digital cross connects  
• Optical transceiver modules  
Available in VFQFPN package  
FUNCTIONALBLOCKDIAGRAM  
PLLBW1  
PLLBW0  
QREG  
QREG  
CLKIN  
CLKIN  
INPUT  
MUX  
DIVN  
DIVM  
PLL  
QOUT  
QOUT  
CONTROL  
LOGIC  
LOCK,  
FREQ.  
DETECTOR  
REFIN  
REFIN  
PD  
SELMODE  
LOCK  
CLK/  
REF0  
CLK/  
REF1  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
NOVEMBER 2004  
1
c
2004 Integrated Device Technology, Inc.  
DSC 6195/27  

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