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5T9820NLI8 PDF预览

5T9820NLI8

更新时间: 2024-11-02 14:50:27
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
36页 238K
描述
Clock Driver, PQCC68

5T9820NLI8 技术参数

是否Rohs认证:不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.92
Is Samacsys:NJESD-30 代码:S-PQCC-N68
JESD-609代码:e0最大I(ol):0.008 A
湿度敏感等级:3端子数量:68
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCN
封装等效代码:LCC68,.4SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER电源:2.5 V
认证状态:Not Qualified子类别:Clock Drivers
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUADBase Number Matches:1

5T9820NLI8 数据手册

 浏览型号5T9820NLI8的Datasheet PDF文件第2页浏览型号5T9820NLI8的Datasheet PDF文件第3页浏览型号5T9820NLI8的Datasheet PDF文件第4页浏览型号5T9820NLI8的Datasheet PDF文件第5页浏览型号5T9820NLI8的Datasheet PDF文件第6页浏览型号5T9820NLI8的Datasheet PDF文件第7页 
IDT5T9820  
EEPROM PROGRAMMABLE  
2.5V ZERO DELAY PLL  
CLOCK DRIVER  
FEATURES:  
DESCRIPTION:  
• 2.5VDD  
The IDT5T9820 is a 2.5V PLL clock driver intended for high perfor-  
mancecomputinganddata-communicationsapplications. TheIDT5T9820  
hastenoutputsinfivebanksoftwo, plusadedicateddifferentialfeedback.  
The redundant input capability allows for a smooth change over to a  
secondary clock source when the primary clock source is absent.  
TheclockdrivercanbeconfiguredthroughtheuseofJTAG/I2Cprogram-  
ming. An internal EEPROM will allow the user to save and restore the  
configurationofthedevice.  
• 5 pairs of outputs  
• Low skew: 100ps all outputs at same interface level, 250ps all  
outputs at different interface levels  
• Selectable positive or negative edge synchronization  
• Tolerant of spread spectrum input clock  
• Synchronous output enable  
• Selectable inputs  
• Input frequency: 4.17MHz to 250MHz  
• Output frequency: 12.5MHz to 250MHz  
• Internal non-volatile EEPROM  
The feedback bank allows divide-by-functionality from 1 to 12 through  
theuseofJTAGorI2Cprogramming. Thisprovidestheuserwithfrequency  
multiplication1to12withoutusingdividedoutputsforfeedback. Eachoutput  
bank also allows for a divide-by functionality of 2 or 4.  
• JTAG or I2C bus serial interface for programming  
• Hot insertable and over-voltage tolerant inputs  
• Feedback divide selection with multiply ratios of (1-6, 8, 10, 12)  
• Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input  
interface  
The IDT5T9820 features a user-selectable, single-ended or differential  
inputtotensingle-endedoutputs. Theclockdriveralsoactsasatranslatorfrom  
a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended  
1.8V/2.5VLVTTLinputtoHSTL,eHSTL,or1.8V/2.5VLVTTLoutputs. Each  
output bank can be individually configured to be either HSTL, eHSTL, 2.5V  
LVTTL,or1.8VLVTTL,includingthefeedbackbank. Also,eachclockinput  
can be individually configured to accept 2.5V LVTTL, 1.8V LVTTL, or  
differentialsignals. Theoutputscanbesynchronouslyenabled/disabled.  
Furthermore, alltheoutputscanbesynchronizedwiththepositiveedge  
of the REF clock input or the negative edge of REF.  
• Selectable HSTL, eHSTL, or 1.8V/2.5V LVTTL output interface for  
each output bank  
• Selectable differential or single-ended inputs and ten single-  
ended outputs  
• PLL bypass for DC testing  
• External differential feedback, internal loop filter  
• Low Jitter: <75ps cycle-to-cycle, all outputs at same interface  
level: <100ps cycle-to-cycle all outputs at different interface  
levels  
• Power-down mode  
• Lock indicator  
• Available in VFQFPN package  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
NOVEMBER 2004  
1
c
2004 Integrated Device Technology, Inc.  
DSC - 6503/21  

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