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5T9891NLI8 PDF预览

5T9891NLI8

更新时间: 2024-01-06 20:04:47
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
37页 280K
描述
Clock Driver, 5T Series, 5 True Output(s), 0 Inverted Output(s), PQCC68, PLASTIC, VFQFN-68

5T9891NLI8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFN包装说明:VQCCN,
针数:68Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.92系列:5T
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQCC-N68
JESD-609代码:e0长度:10 mm
逻辑集成电路类型:CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:68实输出次数:5
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:VQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, VERY THIN PROFILE峰值回流温度(摄氏度):240
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.1 ns
座面最大高度:1 mm最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
最小 fmax:250 MHzBase Number Matches:1

5T9891NLI8 数据手册

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EEPROM PROGRAMMABLE 2.5V  
IDT5T9891  
PROGRAMMABLE SKEW PLL  
DIFFERENTIAL CLOCK DRIVER  
FEATURES:  
DESCRIPTION:  
• 2.5VDD  
The IDT5T9891is a 2.5VPLLdifferentialclockdriverintendedforhigh  
performance computing and data-communications applications. A key  
featureoftheprogrammableskewis theabilityofoutputs toleadorlagthe  
REFinputsignal.TheIDT5T9891has sixdifferentialprogrammableskew  
outputsinsixbanks,includingadedicateddifferentialfeedbackthroughthe  
• 6 pairs of programmable skew outputs  
Low skew: 100ps all outputs at same interface level, 250ps all  
outputs at different interface levels  
• Selectable positive or negative edge synchronization  
Tolerant of spread spectrum input clock  
• Synchronous output enable  
2
use ofJTAGorI Cprogramming. The redundantinputcapabilityallows  
fora smoothchange overtoa secondaryclocksource whenthe primary  
clocksource is absent.  
• Selectable inputs  
Input frequency: 4.17MHz to 250MHz  
• Output frequency: 12.5MHz to 250MHz  
Internal non-volatile EEPROM  
TheclockdrivercanbeconfiguredthroughtheuseofJTAG/I2Cprogram-  
ming. An internal EEPROM will allow the user to save and restore the  
configurationofthedevice.  
2
• JTAG or I C bus serial interface for programming  
The feedbackbankallows divide-by-functionalityfrom1to12through  
2
Hot insertable and over-voltage tolerant inputs  
• Feedback divide selection with multiply ratios of (1-6, 8, 10, 12)  
• Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input  
interface  
• Selectable HSTL, eHSTL, or 1.8V/2.5V LVTTL output interface for  
each output bank  
• Selectable differential or single-ended inputs and six differen-  
tial outputs  
• PLL bypass for DC testing  
• External differential feedback, internal loop filter  
Low Jitter: <75ps cycle-to-cycle, all outputs at same interface  
level: <100ps cycle-to-cycle all outputs at different interface  
levels  
theuseofJTAGorI Cprogramming. Thisprovidestheuserwithfrequency  
multiplication1to12withoutusingdividedoutputsforfeedback. Eachoutput  
bank also allows for a divide-by functionality of 2 or 4.  
The IDT5T9891 features a user-selectable, single-ended or differential  
input to six differential outputs. The differential clock driver also acts as a  
translatorfromadifferentialHSTL,eHSTL,1.8V/2.5VLVTTL,LVEPECL,or  
single-ended1.8V/2.5VLVTTLinputtoHSTL,eHSTL,or1.8V/2.5VLVTTL  
outputs. EachoutputbankcanbeindividuallyconfiguredtobeeitherHSTL,  
eHSTL,2.5VLVTTL,or1.8VLVTTL,includingthefeedbackbank. Also,each  
clockinputcanbeindividuallyconfiguredtoaccept2.5VLVTTL,1.8VLVTTL,  
ordifferentialsignals. Theoutputscanbesynchronouslyenabled/disabled.The  
differentialoutputscanbesynchronouslyenabled/disabled.  
Furthermore,alltheoutputscanbesynchronizedwiththepositiveedge  
of the REF clock input or the negative edge of REF.  
• Power-down mode  
Lock indicator  
Available in VFQFPN package  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
NOVEMBER 2004  
1
c
2004 Integrated Device Technology, Inc.  
DSC - 6505/19  

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