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5T93GL10NLGI PDF预览

5T93GL10NLGI

更新时间: 2024-11-02 19:48:15
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
18页 967K
描述
VFQFPN-40, Tray

5T93GL10NLGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:VFQFPN
包装说明:6 X 6 MM, 0.925 MM HEIGHT, GREEN, PLASTIC, MO-220VJJD-2, VFQFPN-40针数:40
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
系列:5T输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQCC-N40JESD-609代码:e3
长度:6 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:40
实输出次数:10最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC40,.24SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:2.5 VProp。Delay @ Nom-Sup:2 ns
传播延迟(tpd):2 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.025 ns座面最大高度:1 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:6 mm最小 fmax:650 MHz
Base Number Matches:1

5T93GL10NLGI 数据手册

 浏览型号5T93GL10NLGI的Datasheet PDF文件第2页浏览型号5T93GL10NLGI的Datasheet PDF文件第3页浏览型号5T93GL10NLGI的Datasheet PDF文件第4页浏览型号5T93GL10NLGI的Datasheet PDF文件第5页浏览型号5T93GL10NLGI的Datasheet PDF文件第6页浏览型号5T93GL10NLGI的Datasheet PDF文件第7页 
2.5V LVDS, 1:10 GLITCHLESS CLOCK BUFFER  
TERABUFFER™ II  
IDT5T93GL10  
General Description  
Features  
The IDT5T93GL10 2.5V differential clock buffer is a  
Guaranteed low skew: <25ps (maximum)  
S
IC  
user-selectable differential input to ten LVDS  
outputs . The fanout from a differential input to ten  
LVDS outputs reduces loading on the preceding  
driver and provides an efficient clock distribution  
Very low duty cycle distortion: <100ps (maximum)  
High speed propagation delay: <2ns (maximum)  
Up to 650MHz operation  
HiPerClockS™  
network. The IDT5T93GL10 can act as a translator from a  
differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),  
CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V  
LVTTL input can also be used to translate to LVDS outputs. The  
redundant input capability allows for a glitchless change-over  
from a primary clock source to a secondary clock source.  
Selectable inputs are controlled by SEL. During the switchover,  
the output will disable low for up to three clock cycles of the  
previously-selected input clock. The outputs will remain low for up  
to three clock cycles of the newly-selected clock, after which the  
outputs will start from the newly-selected input. A FSEL pin has  
been implemented to control the switchover in cases where a  
clock source is absent or is driven to DC levels below the minimum  
specifications.  
Glitchless input clock switching  
Selectable inputs  
Hot insertable and over-voltage tolerant inputs  
3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL  
(3.3V), CML or LVDS input interfaces  
Selectable differential inputs to ten LVDS outputs  
Power-down mode  
At power-up, FSEL should be LOW  
2.5V VDD  
-40°C to 85°C ambient operating temperature  
Available in VFQFPN package  
Recommends IDT5T9310 if glitchless input selection is not  
The IDT5T93GL10 outputs can be asynchronously  
enabled/disabled. When disabled, the outputs will drive to the  
value selected by the GL pin. Multiple power and grounds reduce  
noise.  
required  
Block Diagram  
GL  
G1  
Q1  
Q1  
Applications  
OUTPUT  
CONTROL  
Clock distribution  
Pin Assignment  
PD  
Q2  
Q2  
OUTPUT  
CONTROL  
A1  
A1  
1
Q3  
Q3  
OUTPUT  
CONTROL  
40 39 38 37 36 35 34 33 32 31  
A2  
A2  
Q4  
Q4  
OUTPUT  
CONTROL  
0
G1  
1
2
3
4
5
G2  
30  
VDD  
GND  
Q1  
29 PD  
VDD  
28  
SEL  
FSEL  
G2  
Q5  
Q5  
OUTPUT  
CONTROL  
27 Q7  
26  
Q1  
Q7  
25  
24 Q6  
VDD  
22 A2  
A2  
Q2  
6
Q6  
Q6  
Q6  
OUTPUT  
CONTROL  
Q2  
7
VDD  
A1  
8
23  
Q7  
Q7  
OUTPUT  
CONTROL  
9
10  
A1  
21  
11 12 13 14 15 16 17 18 19 20  
Q8  
Q8  
OUTPUT  
CONTROL  
Q9  
Q9  
OUTPUT  
CONTROL  
IDT5T93GL10  
40-Lead VFQFPN  
6mm x 6mm x 0.925mm package body  
Q10  
Q10  
OUTPUT  
CONTROL  
K package  
Top View  
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
1
IDT5T93GL10 REV. A MARCH 18, 2009  

5T93GL10NLGI 替代型号

型号 品牌 替代类型 描述 数据表
854110AKILFT IDT

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2.5V Differential LVDS Clock Buffer
854110AKILF IDT

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2.5V Differential LVDS Clock Buffer

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