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5T9304PG PDF预览

5T9304PG

更新时间: 2024-01-14 04:38:35
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 394K
描述
Low Skew Clock Driver, 5T Series, 8 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 1 MM HEIGHT, MO-153, TSSOP-24

5T9304PG 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:4.40 X 7.80 MM, 1 MM HEIGHT, MO-153, TSSOP-24
针数:24Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.62系列:5T
输入调节:DIFFERENTIAL MUXJESD-30 代码:R-PDSO-G24
JESD-609代码:e0长度:7.8 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:24实输出次数:8
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP24,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
电源:2.5 VProp。Delay @ Nom-Sup:1.75 ns
传播延迟(tpd):1.75 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:4.4 mm
Base Number Matches:1

5T9304PG 数据手册

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LVDS, 1:4 Clock Buffer Terabuffer™  
IDT5T9304  
NRND  
DATA SHEET  
NRND – Not Recommend for New Designs  
General Description  
Features  
The IDT5T9304 differential clock buffer has a user-selectable  
differential input to four LVDS outputs. The fanout from a differential  
input to four LVDS outputs reduces loading on the preceding driver  
and provides an efficient clock distribution network. The IDT5T9304  
can act as a translator from a differential HSTL, eHSTL, LVEPECL  
(2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A  
single-ended 3.3V / 2.5V LVTTL input can also be used to translate  
to LVDS outputs. The redundant input capability allows for an  
asynchronous change-over from a primary clock source to a  
secondary clock source. Selectable reference inputs are controlled  
by SEL.  
Guaranteed low skew: 50ps (maximum)  
Very low duty cycle distortion: 125ps (maximum)  
Propagation delay: 1.75ns (maximum)  
Up to 450MHz operation  
Selectable inputs  
Hot insertable and over-voltage tolerant inputs  
3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V),  
LVPECL (3.3V), CML or LVDS input interface  
Selectable differential inputs to four LVDS outputs  
2.5V VDD  
0°C to 70°C ambient operating temperature  
Available in standard (RoHS 5) and lead-free (RoHS 6) packages  
NOT RECOMMENDED FOR NEW DESIGNS  
The IDT5T9304 outputs can be asynchronously enabled/disabled.  
When disabled, the outputs will drive to the value selected by the GL  
pin. Multiple power and grounds reduce noise.  
Applications  
Clock distribution  
Pin Assignment  
A2  
A2  
GND  
PD  
1
2
24  
23  
GND  
VDD  
RESERVED  
VDD  
3
4
22  
21  
5
6
7
8
20  
19  
18  
17  
Q3  
Q3  
Q4  
Q1  
Q1  
Q2  
Q4  
Q2  
VDD  
SEL  
G
VDD  
GL  
A1  
9
16  
15  
14  
13  
10  
11  
12  
GND  
A1  
IDT5T9304  
24-Lead TSSOP  
4.4mm x 7.8mm x 1.0mm package body  
G Package  
Top View  
IDT5T9304 REVISION A MAY 16, 2013  
1
©2013 Integrated Device Technology, Inc.  

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