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5T93GL02PGGI8 PDF预览

5T93GL02PGGI8

更新时间: 2024-02-28 23:50:21
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
17页 184K
描述
Low Skew Clock Driver, 5T Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, GREEN, TSSOP-20

5T93GL02PGGI8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:GREEN, TSSOP-20针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.69
系列:5T输入调节:DIFFERENTIAL MUX
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:6.5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:20
实输出次数:2最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:2.5 V
Prop。Delay @ Nom-Sup:2.2 ns传播延迟(tpd):2.2 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.05 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mm最小 fmax:450 MHz
Base Number Matches:1

5T93GL02PGGI8 数据手册

 浏览型号5T93GL02PGGI8的Datasheet PDF文件第2页浏览型号5T93GL02PGGI8的Datasheet PDF文件第3页浏览型号5T93GL02PGGI8的Datasheet PDF文件第4页浏览型号5T93GL02PGGI8的Datasheet PDF文件第5页浏览型号5T93GL02PGGI8的Datasheet PDF文件第6页浏览型号5T93GL02PGGI8的Datasheet PDF文件第7页 
2.5V LVDS, 1:2 Glitchless Clock Buffer  
TERABUFFER™ II  
5T93GL02  
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 DATA SHEET  
General Description  
Features  
The 5T93GL02 2.5V differential clock buffer is a user-selectable  
differential input to two LVDS outputs. The fanout from a differential  
input to two LVDS outputs reduces loading on the preceding driver  
and provides an efficient clock distribution network. The 5T93GL02  
can act as a translator from a differential HSTL, eHSTL, LVEPECL  
(2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A  
single-ended 3.3V / 2.5V LVTTL input can also be used to translate  
to LVDS outputs. The redundant input capability allows for a  
glitchless change-over from a primary clock source to a secondary  
clock source up to 450MHz. Selectable inputs are controlled by SEL.  
During the switchover, the output will disable low for up to three clock  
cycles of the previously-selected input clock. The outputs will remain  
low for up to three clock cycles of the newly-selected clock, after  
which the outputs will start from the newly-selected input. A FSEL  
pin has been implemented to control the switchover in cases where  
a clock source is absent or is driven to DC levels below the minimum  
specifications.  
Guaranteed low skew: <50ps (maximum)  
Very low duty cycle distortion: <100ps (maximum)  
High speed propagation delay: <2.2ns (maximum)  
Up to 450MHz operation  
Selectable inputs  
Hot insertable and over-voltage tolerant inputs  
3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL  
(3.3V), CML or LVDS input interface  
Selectable differential inputs to two LVDS outputs  
Power-down mode  
At power-up, FSEL should be LOW  
2.5V VDD  
-40°C to 85°C ambient operating temperature  
Available in TSSOP package  
The 5T93GL02 outputs can be asynchronously enabled/disabled.  
When disabled, the outputs will drive to the value selected by the GL  
pin. Multiple power and grounds reduce noise.  
Recommends IDT5T9302 if glitchless input selection is not  
required  
Not Recommended for New Designs  
For functional replacement use 8SLVP1102  
Applications  
Clock distribution  
Pin Assignment  
A2  
A2  
GND  
PD  
1
2
20  
19  
GND  
VDD  
3
4
18  
17  
FSEL  
VDD  
5
6
16 Q2  
15 Q2  
Q1  
Q1  
VDD  
GL  
A1  
VDD  
7
14  
13  
12  
11  
8
SEL  
G
GND  
9
10  
A1  
20-Lead TSSOP  
4.4mm x 6.5mm x 0.925mm package body  
G Package  
Top View  
5T93GL02 Rev A 3/11/15  
1
©2015 Integrated Device Technology, Inc.  

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