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5T9310NLI PDF预览

5T9310NLI

更新时间: 2024-11-11 17:54:39
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
15页 155K
描述
Clock Driver, PQCC40

5T9310NLI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:ObsoleteReach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.87JESD-30 代码:S-PQCC-N40
JESD-609代码:e0湿度敏感等级:3
端子数量:40最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCN封装等效代码:LCC40,.24SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):225电源:2.5 V
Prop。Delay @ Nom-Sup:1.7 ns认证状态:Not Qualified
子类别:Clock Drivers标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30Base Number Matches:1

5T9310NLI 数据手册

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2.5V LVDS 1:10 CLOCK BUFFER  
TERABUFFER™ II  
IDT5T9310  
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015  
DESCRIPTION:  
FEATURES:  
The IDT5T9310 2.5V differential clock buffer is a user-selectable  
differential input to ten LVDS outputs. The fanout from a differential input  
to ten LVDS outputs reduces loading on the preceding driver and provides  
an efficient clock distribution network. The IDT5T9310 can act as a  
translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL  
(3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V  
LVTTL input can also be used to translate to LVDS outputs. The redundant  
input capability allows for an asynchronous change-over from a primary  
clock source to a secondary clock source. Selectable reference inputs are  
controlled by SEL.  
• Guaranteed Low Skew < 25ps (max)  
• Very low duty cycle distortion < 125ps (max)  
• High speed propagation delay < 1.75ns (max)  
• Up to 1GHz operation  
• Selectable inputs  
• Hot insertable and over-voltage tolerant inputs  
• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL  
(3.3V), CML, or LVDS input interface  
• Selectable differential inputs to ten LVDS outputs  
• Power-down mode  
TheIDT5T9310outputscanbeasynchronouslyenabled/disabled. When  
disabled, the outputs will drive to the value selected by the GL pin. Multiple  
power and grounds reduce noise.  
• 2.5V VDD  
• Available in VFQFPN package  
APPLICATIONS:  
• Clock distribution  
FUNCTIONAL BLOCK  
DIAGRAM  
GL  
G1  
Q1  
OUTPUT  
CONTROL  
Q1  
PD  
Q2  
Q2  
OUTPUT  
CONTROL  
A1  
A1  
1
0
Q3  
Q3  
OUTPUT  
CONTROL  
A2  
A2  
Q4  
Q4  
OUTPUT  
CONTROL  
SEL  
G2  
Q5  
Q5  
OUTPUT  
CONTROL  
Q6  
Q6  
OUTPUT  
CONTROL  
Q7  
Q7  
OUTPUT  
CONTROL  
Q8  
Q8  
OUTPUT  
CONTROL  
Q9  
Q9  
OUTPUT  
CONTROL  
Q10  
Q10  
OUTPUT  
CONTROL  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JANUARY 2014  
1
© 2014 Integrated Device Technology, Inc.  
DSC-6175/18  

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