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2SK3866G-T

更新时间： 2024-02-15 16:38:05
品牌 Logo 应用领域
松下 - PANASONIC 开关光电二极管晶体管
页数 文件大小 规格书
4页 408K
描述
Small Signal Field-Effect Transistor, 0.00022A I(D), 20V, 1-Element, N-Channel, Silicon, Junction FET, ROHS COMPLIANT, TSSSMINI3-F2, 3 PIN

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2SK3866G-T 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：SMALL OUTLINE, R-PDSO-F3针数：3
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8541.21.00.95风险等级：5.84
其他特性：LOW NOISE配置：SINGLE
最小漏源击穿电压：20 V最大漏极电流 (ID)：0.00022 A
FET 技术：JUNCTIONJESD-30 代码：R-PDSO-F3
元件数量：1端子数量：3
工作模式：DEPLETION MODE封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED极性/信道类型：N-CHANNEL
认证状态：Not Qualified表面贴装：YES
端子形式：FLAT端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED晶体管应用：SWITCHING
晶体管元件材料：SILICONBase Number Matches：1

2SK3866G-T 数据手册

 浏览型号2SK3866G-T的Datasheet PDF文件第2页浏览型号2SK3866G-T的Datasheet PDF文件第3页浏览型号2SK3866G-T的Datasheet PDF文件第4页 
This product complies with the RoHS Directive (EU 2002/95/EC).  
Silicon Junction FETs (Small Signal)  
2SK3866  
Silicon N-channel junction FET  
For impedance conversion in low frequency  
For electret capacitor microphone  
Package  
Features  
ꢀCode  
Low noise voltage NV  
High voltage gain GV  
Thin package: TSSSMini3-F1 (1.2 mm × 1.2 mm × 0.33 mm)  
TSSSMini3-F1  
ꢀPin Name  
1: rain  
Absolute Maximum Ratings Ta = 25°C  
ce  
Parameter  
Drain-source voltage (Gate open)  
Drain-gate voltage (Souece open)  
Drain-source current (Gate open)  
Drain-gate current (Souece open)  
Power dissipation  
Symbol  
VDSO  
VDGO  
IDO  
Ratin
Unit  
V
20  
Marking Symbol: 4S  
V
mA  
mA  
mW  
°C  
IDG
2
100  
PD  
Channel temperature  
T
c
125  
Storage temperature  
T
stg  
–5 to +125  
°C  
Electrical Characteristics Ta = 25°C±
Paame
Sym
ID  
Conditions  
Min  
100  
107  
660  
Typ  
Max  
330  
310  
Unit  
mA  
mA  
mS  
1
Drain current *  
VDD = 2.0 V, Rd = 2.2 kW ± 1%  
VDD = 2.0 V, Rd = 2.2 kW ± 1%, VGS = 0  
VDS = 2.0 V, VGS = 0, f = 1 kHz  
2
ain-sourccurrnt *  
IDSS  
gm  
Mutual conduance  
1500  
VDD = 2.0 V, Rd = 2.2 kW ± 1%  
CO = 5 pF, A-curve  
3
Noise voltage *  
NV  
GV1  
GV2  
GV3  
8
mV  
VDD = 2.0 V, Rd = 2.2 kW ± 1%  
CO = 5 pF, eG = 10 mV, f = 1 kHz  
–5.0  
–3.0  
–7.0  
–1.0  
3.0  
VDD = 12 V, Rd = 2.2 kW ± 1%  
CO = 5 pF, eG = 10 mV, f = 1 kHz  
Voltage gain  
dB  
dB  
VDD = 1.5 V, Rd = 2.2 kW ± 1%  
CO = 5 pF, eG = 10 mV, f = 1 kHz  
–1.5  
VD= 2.0 V, Rd = 2.2 kW ± 1%  
CO = 5 pF, eG = 10 mV  
f = 1 kHz to 70 Hz  
4
DGV . f*  
0.0  
0.5  
1.7  
1.0  
Voltage gain difference  
GV1 – GV3  
Note) 1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS C 7030 measuring methods for transistors.  
2. A protection diode is built-in between gate and source of transistor. However if forward current flows between gate and source transistor  
might be damaged. So please be careful not insert reverse.  
3. *1: ID is assured for IDSS  
.
2: Rank classification  
*
Rank  
S
T
ID (mA)  
100 to 220  
107 to 210  
180 to 330  
190 to 310  
IDSS (mA)  
3: NV is assured for design.  
*
*
4: D|GV . f | is assured for AQL 0.065. (The measurement method is used by source-grounded circuit.)  
Publication date: August 2008  
SJF00095CED  
1
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