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XCR3256XL-7CS280C PDF预览

XCR3256XL-7CS280C

更新时间: 2024-11-12 22:41:19
品牌 Logo 应用领域
赛灵思 - XILINX /
页数 文件大小 规格书
10页 239K
描述
256 Macrocell CPLD

XCR3256XL-7CS280C 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:BGA
包装说明:TFBGA, BGA280,19X19,32针数:280
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.13
其他特性:YES最大时钟频率:154 MHz
系统内可编程:YESJESD-30 代码:S-PBGA-B280
JESD-609代码:e0JTAG BST:YES
长度:16 mm湿度敏感等级:3
专用输入次数:I/O 线路数量:164
宏单元数:256端子数量:280
最高工作温度:70 °C最低工作温度:
组织:0 DEDICATED INPUTS, 164 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA280,19X19,32封装形状:SQUARE
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):240
电源:3.3 V可编程逻辑类型:EE PLD
传播延迟:7.5 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Programmable Logic Devices
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn63Pb37)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:16 mm
Base Number Matches:1

XCR3256XL-7CS280C 数据手册

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XCR3256XL 256 Macrocell CPLD  
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DS013 (v1.2) May 3, 2000  
Preliminary Product Specification  
Features  
Description  
7.5 ns pin-to-pin logic delays  
The XCR3256XL is a 3.3V, 256 macrocell CPLD targeted at  
power sensitive designs that require leading edge program-  
mable logic solutions. A total of 16 logic blocks provide  
6,000 usable gates. Pin-to-pin propagation delays are  
7.5 ns with a maximum system frequency of 140 MHz.  
System frequencies up to 140 MHz  
256 macrocells with 6,000 usable gates  
Available in small footprint packages  
-
-
-
144-pin TQFP (116 user I/O pins)  
208-pin PQFP (160 user I/O)  
280-ball CS BGA (160 user I/O)  
TotalCMOS™ Design Technique for  
Fast Zero Power  
Xilinx offers a TotalCMOS CPLD, both in process technol-  
ogy and design technique. Xilinx employs a cascade of  
CMOS gates to implement its sum of products instead of  
the traditional sense amp approach. This CMOS gate  
implementation allows Xilinx to offer CPLDs that are both  
high performance and low power, breaking the paradigm  
that to have low power, you must have low performance.  
Refer to Figure 1 and Table 1 showing the ICC vs. Fre-  
quency of our XCR3256XL TotalCMOS CPLD (data taken  
with 16 up/down, loadable 16-bit counters at 3.3V, 25 C).  
Optimized for 3.3V systems  
-
-
-
Ultra low power operation  
5V tolerant I/O pins with 3.3V core supply  
Advanced 0.35 micron five metal layer re-  
programmable process  
-
FZP™ CMOS design technology  
Advanced system features  
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-
-
-
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In-system programming  
Input registers  
Predictable timing model  
Up to 23 clocks available per logic block  
Excellent pin retention during design changes  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
Four global clocks  
Eight product term control terms per logic block  
Fast ISP programming times  
Port Enable pin for additional I/O  
2.7V to 3.6V industrial grade voltage range  
Programmable slew rate control per output  
Security bit prevents unauthorized access  
Refer to XPLA3 family data sheet (DS012) for  
architecture description  
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at  
http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners.  
All specifications are subject to change without notice.  
DS013 (v1.2) May 3, 2000  
www.xilinx.com  
1
Preliminary Product Specification  
1-800-255-7778  

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