Datasheet > XCR3320-8BG256I

XCR3320-8BG256I

更新时间： 2024-11-13 20:00:43

品牌	Logo	应用领域
赛灵思 - XILINX		时钟输入元件可编程逻辑
页数	文件大小	规格书
43页	392K
描述
Loadable PLD, 8.5ns, 320-Cell, CMOS, PBGA256, PLASTIC, BGA-256

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XCR3320-8BG256I 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	PLASTIC, BGA-256
针数：	256	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	5.92
其他特性：	YES	最大时钟频率：	95 MHz
系统内可编程：	YES	JESD-30 代码：	S-PBGA-B256
JESD-609代码：	e0	JTAG BST：	YES
长度：	27 mm	湿度敏感等级：	3
专用输入次数：	12	I/O 线路数量：	3
宏单元数：	320	端子数量：	256
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	12 DEDICATED INPUTS, 3 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA256,20X20,50	封装形状：	SQUARE
封装形式：	GRID ARRAY	电源：	3.3 V
可编程逻辑类型：	LOADABLE PLD	传播延迟：	8.5 ns
认证状态：	Not Qualified	座面最大高度：	2.55 mm
子类别：	Programmable Logic Devices	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn63Pb37)
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	宽度：	27 mm
Base Number Matches：	1

XCR3320-8BG256I 数据手册

APPLICATION NOTE

This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details.

XCR3320: 320 Macrocell SRAM

CPLD

DS033 (v1.3) October 9, 2000

0* Product Specification

nique is also what allows Xilinx to offer a true CPLD archi-

tecture in a high density device.

Features

•

320 macrocell SRAM based CPLD

Configuration times of under 1.0 second

IEEE 1149.1 compliant JTAG testing capability

The Xilinx XCR3320 devices use the patented XPLA2

(eXtended Programmable Logic Array) architecture. This

architecture combines the best features of both PAL- and

PLA-type logic structures to deliver high speed and flexible

logic allocation that results in superior ability to make

design changes with fixed pinouts. The XPLA2 architecture

is constructed from 80 macrocell Fast Modules that are

connected together by an interconnect array. Within each

Fast Module are four Logic Blocks of 20 macrocells each.

Each Logic Block contains a PAL structure with four dedi-

cated product terms for each macrocell. In addition, each

Logic Block has 32 additional product terms in a PLA struc-

ture that can be shared through a fully programmable OR

array to any of the 20 macrocells. This combination effi-

ciently allocates logic throughout the Logic Block, which

increases device density and allows for design changes

without re-defining the pinout or changing the system tim-

ing. The XCR3320 offers pin-to-pin propagation delays of

7.5 ns through the PAL array of a Fast Module; and if the

PLA array is used, an additional 1.5 ns is added to the

delay, no matter how many PLA product terms are used. If

the interconnect array between Fast Modules is used, there

is a second fixed delay of 2.0 ns. This means that the worst

case pin-to-pin propagation delay within a fast module is

7.5 + 1.5 = 9.0 ns, and the delay from any pin to any other

pin across the entire chip is 7.5 + 2.0 = 9.5 ns if only the

PAL array is used, and 7.5 + 1.5 + 2.0 = 11.0 ns if the PLA

array is used.

Five pin JTAG interface

IEEE 1149.1 TAP controller

•

In system configurable

3.3V device with 5V tolerant I/O

Innovative XPLA2 Architecture combines extreme

flexibility and high speeds

•

Eight synchronous clock networks with programmable

polarity at every macrocell

Up to 32 asynchronous clocks support complex

clocking needs

Innovative XOR structure at every macrocell provides

excellent logic reduction capability

Logic expandable to 36 product terms on a single

macrocell

•

Advanced 0.35µ SRAM process

Design entry and verification using industry standard

and Xilinx CAE tools

•

Control Term structure provides either sum terms or

product terms in each logic block for:

3-state buffer control

Asynchronous macrocell register reset/preset

•

Global 3-state pin facilitates "bed of nails" testing

without sacrificing logic resources

Programmable slew rate control

Small form factor packages with high I/O counts

Available in commercial and industrial temperature

ranges

•

Each macrocell also has a two input XOR gate with the

dedicated PAL product terms on one input and the PLA

product terms on the other input. This patent-pending Ver-

satile XOR structure allows for very efficient logic optimiza-

tion compared to competing XOR structures that have only

one product term as the second input to the XOR gate. The

Versatile XOR allows an 8-bit XOR function to be imple-

mented in only 20 product terms, compared to 65 product

terms for the traditional XOR approach.

Description

The XCR3320 device is a member of the CoolRunner^®

family of high-density SRAM-based CPLDs (Complex Pro-

grammable Logic Device) from Xilinx. This device com-

bines high speed and deterministic pin-to-pin timing with

high density. The XCR3320 uses the patented Fast Zero

Power (FZP™) design technique that combines high speed

and low power for the first time ever in a CPLD. FZP allows

the XCR3320 to have true pin-to-pin timing delays of 7.5

ns, and standby currents of 100 µA without the need for

`turbo bits' or other power down schemes. By replacing

conventional sense amplifier methods for implementing

product terms (a technique that has been used since the

bipolar era) with a cascaded chain of pure CMOS gates,

both standby and dynamic power are dramatically reduced

when compared to other CPLDs. The FZP design tech-

The XCR3320 is SRAM-based, which means that it is con-

figured from an external source at power up. See the con-

figuration section of this data sheet for more information.

The device supports the full JTAG specification (IEEE

1149.1) through an industry standard JTAG interface. It can

also be configured through the JTAG port, which is very

useful for prototyping. See section titled “Device Configura-

tion Through JTAG” on page 29 for more information.

DS033 (v1.3) October 9, 2000

www.xilinx.com

1-800-255-7778

12 3 4 5 6 7...43

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与XCR3320-8BG256I相关器件

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