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XCR3384XL-10TQG144I

更新时间： 2024-11-13 04:23:43
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赛灵思 - XILINX /
页数 文件大小 规格书
13页 227K
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384 Macrocell CPLD

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XCR3384XL-10TQG144I 数据手册

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XCR3384XL: 384 Macrocell CPLD  
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14  
DS024 (v2.0) March 31, 2006  
Product Specification  
Features  
Description  
•
•
•
•
•
Low power 3.3V 384 macrocell CPLD  
The CoolRunner™ XPLA3 XCR3384XL device is a 3.3V,  
384 macrocell CPLD targeted at power sensitive designs  
that require leading edge programmable logic solutions. A  
total of 24 function blocks provide 9,000 usable gates.  
Pin-to-pin propagation delays are as fast as 7.0 ns with a  
maximum system frequency of 135 MHz.  
7.0 ns pin-to-pin logic delays  
System frequencies up to 135 MHz  
384 macrocells with 9,000 usable gates  
Available in small footprint packages  
-
-
-
-
144-pin TQFP (118 user I/O)  
208-pin PQFP (172 user I/O)  
256-ball FBGA (212 user I/O)  
324-ball FBGA (220 user I/O)  
TotalCMOS Design Technique for Fast  
Zero Power  
CoolRunner XPLA3 CPLDs offer a TotalCMOS™ solution,  
both in process technology and design technique. These  
CPLDs employ a cascade of CMOS gates to implement  
their sum of products, instead of the traditional sense amp  
approach. This CMOS gate implementation allows Xilinx to  
offer CPLDs that are both high performance and low power,  
breaking the paradigm that to have low power, you must  
have low performance. Refer to Figure 1 and Table 1 show-  
ing the ICC vs. Frequency of our XCR3384XL TotalCMOS  
CPLD (data taken with 24 resetable up/down, 16-bit  
counters at 3.3V, 25°C).  
•
Optimized for 3.3V systems  
-
-
-
-
Ultra low power operation  
Typical Standby Current of 18 μA at 25°C  
5V tolerant I/O pins with 3.3V core supply  
Advanced 0.35 micron five layer metal EEPROM  
process  
Fast Zero Power™ (FZP) CMOS design  
technology  
3.3V PCI electrical specification compatible outputs  
(no internal clamp diode on any input or I/O)  
-
-
•
Advanced system features  
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-
-
-
-
-
-
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In-system programming  
Input registers  
Predictable timing model  
Up to 23 clocks available per function block  
Excellent pin retention during design changes  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
Four global clocks  
280  
240  
200  
160  
120  
80  
Eight product term control terms per function block  
•
•
•
Fast ISP programming times  
Port Enable pin for additional I/O  
2.7V to 3.6V supply voltage at industrial grade voltage  
range  
40  
•
•
•
Programmable slew rate control per output  
Security bit prevents unauthorized access  
0
Refer to CoolRunner™ XPLA3 family data sheet  
(DS012) for architecture description  
0
20  
40  
60  
Frequency (MHz)  
Figure 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C  
80  
100 120 140  
Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C  
Frequency (MHz)  
0
1
10  
20  
40  
60  
80  
100  
120  
140  
Typical ICC (mA)  
0.018  
2.2  
24.4  
42.4  
82.6  
123.0  
155.6  
187.8  
227.5  
258.1  
© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS024 (v2.0) March 31, 2006  
www.xilinx.com  
1
Product Specification  
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XCR3384XL-10TQG144I 替代型号

型号 品牌 替代类型 描述 数据表
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XCR3384XL-10TQG144C XILINX

完全替代

 384 Macrocell CPLD

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