Datasheet > XCR3384XL_06

XCR3384XL_06

更新时间： 2024-09-25 04:23:43

品牌	Logo	应用领域
赛灵思 - XILINX		/
页数	文件大小	规格书
13页	227K
描述
384 Macrocell CPLD

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XCR3384XL_06 数据手册

XCR3384XL: 384 Macrocell CPLD

DS024 (v2.0) March 31, 2006

Product Specification

Features

Description

•

Low power 3.3V 384 macrocell CPLD

The CoolRunner™ XPLA3 XCR3384XL device is a 3.3V,

384 macrocell CPLD targeted at power sensitive designs

that require leading edge programmable logic solutions. A

total of 24 function blocks provide 9,000 usable gates.

Pin-to-pin propagation delays are as fast as 7.0 ns with a

maximum system frequency of 135 MHz.

7.0 ns pin-to-pin logic delays

System frequencies up to 135 MHz

384 macrocells with 9,000 usable gates

Available in small footprint packages

144-pin TQFP (118 user I/O)

208-pin PQFP (172 user I/O)

256-ball FBGA (212 user I/O)

324-ball FBGA (220 user I/O)

TotalCMOS Design Technique for Fast

Zero Power

CoolRunner XPLA3 CPLDs offer a TotalCMOS™ solution,

both in process technology and design technique. These

CPLDs employ a cascade of CMOS gates to implement

their sum of products, instead of the traditional sense amp

approach. This CMOS gate implementation allows Xilinx to

offer CPLDs that are both high performance and low power,

breaking the paradigm that to have low power, you must

have low performance. Refer to Figure 1 and Table 1 show-

ing the I_CCvs. Frequency of our XCR3384XL TotalCMOS

CPLD (data taken with 24 resetable up/down, 16-bit

counters at 3.3V, 25°C).

•

Optimized for 3.3V systems

Ultra low power operation

Typical Standby Current of 18 μA at 25°C

5V tolerant I/O pins with 3.3V core supply

Advanced 0.35 micron five layer metal EEPROM

process

Fast Zero Power™ (FZP) CMOS design

technology

3.3V PCI electrical specification compatible outputs

(no internal clamp diode on any input or I/O)

•

Advanced system features

In-system programming

Input registers

Predictable timing model

Up to 23 clocks available per function block

Excellent pin retention during design changes

Full IEEE Standard 1149.1 boundary-scan (JTAG)

Four global clocks

280

240

200

160

120

Eight product term control terms per function block

•

Fast ISP programming times

Port Enable pin for additional I/O

2.7V to 3.6V supply voltage at industrial grade voltage

range

•

Programmable slew rate control per output

Security bit prevents unauthorized access

Refer to CoolRunner™ XPLA3 family data sheet

(DS012) for architecture description

Frequency (MHz)

Figure 1: Typical I_CCvs. Frequency at V_CC= 3.3V, 25°C

100 120 140

Table 1: Typical I_CCvs. Frequency at V_CC= 3.3V, 25°C

Frequency (MHz)

100

120

140

Typical I_CC(mA)

0.018

2.2

24.4

42.4

82.6

123.0

155.6

187.8

227.5

258.1

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS024 (v2.0) March 31, 2006

www.xilinx.com

Product Specification

12 3 4 5 6 7...13

中文翻译

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与XCR3384XL_06相关器件

型号	品牌	获取价格	描述	数据表
XCR3384XL_07	XILINX	获取价格	384 Macrocell CPLD
XCR3384XL-10FG324C	XILINX	获取价格	384 Macrocell CPLD
XCR3384XL-10FG324I	XILINX	获取价格	384 Macrocell CPLD
XCR3384XL-10FT256C	XILINX	获取价格	384 Macrocell CPLD
XCR3384XL-10FT256I	XILINX	获取价格	384 Macrocell CPLD
XCR3384XL-10FTG256I	XILINX	获取价格	EE PLD, 10ns, 384-Cell, CMOS, PBGA256, FBGA-256
XCR3384XL-10PQ208C	XILINX	获取价格	384 Macrocell CPLD
XCR3384XL-10PQ208I	XILINX	获取价格	384 Macrocell CPLD
XCR3384XL-10PQG208C	XILINX	获取价格	384 Macrocell CPLD
XCR3384XL-10PQG208I	XILINX	获取价格	384 Macrocell CPLD

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