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XCR3384XL-12PQ208C

更新时间： 2024-09-24 22:17:03
品牌 Logo 应用领域
赛灵思 - XILINX /
页数 文件大小 规格书
12页 95K
描述
384 Macrocell CPLD

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XCR3384XL-12PQ208C 数据手册

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XCR3384XL: 384 Macrocell CPLD  
0
14  
DS024 (v1.3) August 10, 2001  
Advance Product Specification  
Features  
Description  
•
•
•
•
•
Lowest power 384 macrocell CPLD  
The XCR3384XL is a 3.3V, 384 macrocell CPLD targeted at  
power sensitive designs that require leading edge program-  
mable logic solutions. A total of 24 function blocks provide  
9,600 usable gates. Pin-to-pin propagation delays are  
7.5 ns with a maximum system frequency of 127 MHz.  
7.5 ns pin-to-pin logic delays  
System frequencies up to 127 MHz  
384 macrocells with 9,600 usable gates  
Available in small footprint packages  
-
-
-
-
144-pin TQFP (118 user I/O)  
208-pin PQFP (172 user I/O)  
256-ball FBGA (212 user I/O)  
324-ball FBGA (220 user I/O)  
TotalCMOS™ Design Technique for  
Fast Zero Power  
Xilinx offers a TotalCMOS CPLD, both in process technol-  
ogy and design technique. Xilinx employs a cascade of  
CMOS gates to implement its sum of products instead of  
the traditional sense amp approach. This CMOS gate imple-  
mentation allows Xilinx to offer CPLDs that are both high  
performance and low power, breaking the paradigm that to  
have low power, you must have low performance. Refer to  
•
•
Optimized for 3.3V systems  
-
-
-
Ultra low power operation  
5V tolerant I/O pins with 3.3V core supply  
Advanced 0.35 micron five layer metal EEPROM  
process  
FZP™ CMOS design technology  
-
Figure 1 and Table 1 showing the I  
vs. Frequency of our  
CC  
Advanced system features  
XCR3384XL TotalCMOS CPLD (data taken with 24  
up/down, loadable 16-bit counters at 3.3V, 25°C).  
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-
-
-
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-
-
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In-system programming  
Input registers  
Predictable timing model  
Up to 23 clocks available per function block  
Excellent pin retention during design changes  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
Four global clocks  
140  
120  
100  
80  
Eight product term control terms per function block  
•
•
•
Fast ISP programming times  
Port Enable pin for additional I/O  
60  
2.7V to 3.6V supply voltage at industrial grade voltage  
range  
40  
•
•
•
Programmable slew rate control per output  
Security bit prevents unauthorized access  
20  
Refer to XPLA3 family data sheet (DS012) for  
architecture description  
0
0
20 40  
60  
80 100 120 140 160  
Frequency (MHz)  
DS024_01_112700  
Figure 1: XCR3384XL Typical I vs. Frequency at  
CC  
V
= 3.3V, 25°C  
CC  
Table 1: Typical I vs. Frequency at V = 3.3V, 25°C  
CC  
CC  
Frequency (MHz)  
Typical I (mA)  
0
1
10  
TBD  
20  
40  
60  
80  
100  
120  
140  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
CC  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS024 (v1.3) August 10, 2001  
www.xilinx.com  
1
Advance Product Specification  
1-800-255-7778  
 
 
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XCR3384XL-12PQ208C 替代型号

型号 品牌 替代类型 描述 数据表
XCR3384XL-7PQG208C XILINX

完全替代

 384 Macrocell CPLD
XCR3384XL-7PQ208C XILINX

完全替代

 384 Macrocell CPLD
XCR3384XL-10PQ208C XILINX

完全替代

 384 Macrocell CPLD

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