Datasheet > XCR3256XL-7PQ144C

XCR3256XL-7PQ144C

更新时间： 2024-09-24 22:23:11

品牌	Logo	应用领域
赛灵思 - XILINX		/
页数	文件大小	规格书
10页	239K
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256 Macrocell CPLD

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XCR3256XL 256 Macrocell CPLD

DS013 (v1.2) May 3, 2000

Preliminary Product Specification

Features

Description

•

7.5 ns pin-to-pin logic delays

The XCR3256XL is a 3.3V, 256 macrocell CPLD targeted at

power sensitive designs that require leading edge program-

mable logic solutions. A total of 16 logic blocks provide

6,000 usable gates. Pin-to-pin propagation delays are

7.5 ns with a maximum system frequency of 140 MHz.

System frequencies up to 140 MHz

256 macrocells with 6,000 usable gates

Available in small footprint packages

144-pin TQFP (116 user I/O pins)

208-pin PQFP (160 user I/O)

280-ball CS BGA (160 user I/O)

TotalCMOS™ Design Technique for

Fast Zero Power

Xilinx offers a TotalCMOS CPLD, both in process technol-

ogy and design technique. Xilinx employs a cascade of

CMOS gates to implement its sum of products instead of

the traditional sense amp approach. This CMOS gate

implementation allows Xilinx to offer CPLDs that are both

high performance and low power, breaking the paradigm

that to have low power, you must have low performance.

Refer to Figure 1 and Table 1 showing the I_CCvs. Fre-

quency of our XCR3256XL TotalCMOS CPLD (data taken

with 16 up/down, loadable 16-bit counters at 3.3V, 25 C).

•

Optimized for 3.3V systems

Ultra low power operation

5V tolerant I/O pins with 3.3V core supply

Advanced 0.35 micron five metal layer re-

programmable process

FZP™ CMOS design technology

Advanced system features

In-system programming

Input registers

Predictable timing model

Up to 23 clocks available per logic block

Excellent pin retention during design changes

Full IEEE Standard 1149.1 boundary-scan (JTAG)

Four global clocks

Eight product term control terms per logic block

•

Fast ISP programming times

Port Enable pin for additional I/O

2.7V to 3.6V industrial grade voltage range

Programmable slew rate control per output

Security bit prevents unauthorized access

Refer to XPLA3 family data sheet (DS012) for

architecture description

http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners.

All specifications are subject to change without notice.

DS013 (v1.2) May 3, 2000

www.xilinx.com

Preliminary Product Specification

1-800-255-7778

12 3 4 5 6 7...10

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与XCR3256XL-7PQ144C相关器件

型号	品牌	获取价格	描述	数据表
XCR3256XL-7PQ144I	XILINX	获取价格	256 Macrocell CPLD
XCR3256XL-7PQ208C	XILINX	获取价格	256 Macrocell CPLD
XCR3256XL-7PQ208I	XILINX	获取价格	256 Macrocell CPLD
XCR3256XL-7PQ256C	XILINX	获取价格	256 Macrocell CPLD
XCR3256XL-7PQ256I	XILINX	获取价格	256 Macrocell CPLD
XCR3256XL-7PQ280C	XILINX	获取价格	256 Macrocell CPLD
XCR3256XL-7PQ280I	XILINX	获取价格	256 Macrocell CPLD
XCR3256XL-7TQ144C	XILINX	获取价格	256 Macrocell CPLD
XCR3256XL-7TQ144I	XILINX	获取价格	256 Macrocell CPLD
XCR3256XL-7TQG144C	XILINX	获取价格	EE PLD, 7.5ns, 256-Cell, CMOS, PQFP144, LEAD FREE, TQFP-144

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