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XCR3256XLSERIES

更新时间： 2024-09-24 23:32:39
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
12页 114K
描述
256 Macrocell CPLD

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中文翻译

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XCR3256XLSERIES 数据手册

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R
XCR3256XL 256 Macrocell CPLD  
0
14  
DS013 (v1.9) January 8, 2002  
Preliminary Product Specification  
Features  
Description  
•
•
•
•
•
Lowest power 256 macrocell CPLD  
The XCR3256XL is a 3.3V, 256 macrocell CPLD targeted at  
power sensitive designs that require leading edge program-  
mable logic solutions. A total of 16 function blocks provide  
6,000 usable gates. Pin-to-pin propagation delays are  
7.5 ns with a maximum system frequency of 140 MHz.  
7.5 ns pin-to-pin logic delays  
System frequencies up to 140 MHz  
256 macrocells with 6,000 usable gates  
Available in small footprint packages  
-
-
-
-
144-pin TQFP (120 user I/O pins)  
208-pin PQFP (164 user I/O)  
256-ball FBGA (164 user I/O)  
280-ball CS BGA (164 user I/O)  
TotalCMOS Design Technique for Fast  
Zero Power  
Xilinx offers a TotalCMOS CPLD, both in process technol-  
ogy and design technique. Xilinx employs a cascade of  
CMOS gates to implement its sum of products instead of  
the traditional sense amp approach. This CMOS gate imple-  
mentation allows Xilinx to offer CPLDs that are both high  
performance and low power, breaking the paradigm that to  
have low power, you must have low performance. Refer to  
•
•
Optimized for 3.3V systems  
-
-
-
Ultra low power operation  
5V tolerant I/O pins with 3.3V core supply  
Advanced 0.35 micron five layer metal EEPROM  
process  
Fast Zero Power™ (FZP) CMOS design  
technology  
Figure 1 and Table 1 showing the I vs. Frequency of our  
CC  
-
XCR3256XL TotalCMOS CPLD (data taken with 16  
resetable up/down, 16-bit counters at 3.3V, 25°C).  
Advanced system features  
-
-
-
-
-
-
-
-
In-system programming  
Input registers  
Predictable timing model  
Up to 23 clocks available per function block  
Excellent pin retention during design changes  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
Four global clocks  
140  
120  
100  
80  
Eight product term control terms per function block  
•
•
•
Fast ISP programming times  
60  
Port Enable pin for additional I/O  
2.7V to 3.6V supply voltage at industrial grade voltage  
range  
40  
•
•
•
Programmable slew rate control per output  
Security bit prevents unauthorized access  
20  
Refer to XPLA3 family data sheet (DS012) for  
architecture description  
0
20  
40  
60  
Frequency (MHz)  
Figure 1: XCR3256XL Typical I vs. Frequency at  
80  
100 120 140 160  
DS013_01_102401  
CC  
V
= 3.3V, 25°C  
CC  
Table 1: Typical I vs. Frequency at V = 3.3V, 25°C  
CC  
CC  
Frequency (MHz)  
0
1
10  
20  
40  
60  
80  
68  
100  
120  
140  
Typical I (mA)  
0.02  
0.91  
8.87  
17.7  
34.8  
51.5  
84.2  
100.1  
116.6  
CC  
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS013 (v1.9) January 8, 2002  
www.xilinx.com  
1
Preliminary Product Specification  
1-800-255-7778  
1234567...12

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与XCR3256XLSERIES相关器件

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XCR3320-10BG256C XILINX

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 		Loadable PLD, 10ns, 320-Cell, CMOS, PBGA256, PLASTIC, BGA-256
XCR3320-10TQ144C ETC

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XCR3320-10TQ160C XILINX

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 		Loadable PLD, 10ns, 320-Cell, CMOS, PQFP160, PLASTIC, TQFP-160
XCR3320-7BG256C XILINX

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 		Loadable PLD, 7.5ns, 320-Cell, CMOS, PBGA256, PLASTIC, BGA-256
XCR3320-7TQ144C ETC

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XCR3320-7TQ160C XILINX

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 		Loadable PLD, 7.5ns, 320-Cell, CMOS, PQFP160, PLASTIC, TQFP-160
XCR3320-8BG256I XILINX

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 		Loadable PLD, 8.5ns, 320-Cell, CMOS, PBGA256, PLASTIC, BGA-256
XCR3320-8TQ144I ETC

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XCR3320-8TQ160I XILINX

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 		Loadable PLD, 8.5ns, 320-Cell, CMOS, PQFP160, PLASTIC, TQFP-160
XCR3384XL XILINX

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 		384 Macrocell CPLD

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