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W26010AJ-15 PDF预览

W26010AJ-15

更新时间: 2024-11-07 22:14:55
品牌 Logo 应用领域
华邦 - WINBOND /
页数 文件大小 规格书
10页 159K
描述
64K 16 HIGH-SPEED CMOS STATIC RAM

W26010AJ-15 技术参数

生命周期:Obsolete零件包装代码:SOJ
包装说明:SOJ, SOJ44,.44针数:44
Reach Compliance Code:unknownECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.44
最长访问时间:15 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-J44长度:28.58 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:16功能数量:1
端子数量:44字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ44,.44封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
电源:5 V认证状态:Not Qualified
座面最大高度:3.759 mm最大待机电流:0.01 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.26 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
宽度:10.16 mm

W26010AJ-15 数据手册

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W26010A  
´ 16 HIGH-SPEED CMOS STATIC RAM  
64K  
GENERAL DESCRIPTION  
The W26010A is a high-speed, low-power CMOS static RAM organized as 65,536 ´ 16 bits that  
operates on a single 5-volt power supply. This device is manufactured using Winbond's high  
performance CMOS technology.  
The W26010A has an active low chip select, separate upper and lower byte selects, and a fast output  
enable. No clock or refreshing is required. Separate byte select controls (#LB and #UB) allow individual  
bytes to be written and read. #LB controls I/O1-I/O8, the lower byte. #UB controls I/O9- I/O16, the  
upper byte. This device is well suited for use in high-density, high-speed system applications.  
FEATURES  
· High speed access time: 15/20/25 nS (max.)  
· Low power consumption:  
- Active: 1.3W (max.)  
· All inputs and outputs directly TTL compatible  
· Three-state outputs  
· Data byte control  
· Single +5V power supply  
· Fully static operation  
- No clock or refreshing  
- #LB (I/O1- I/O8), #UB (I/O9- I/O16)  
· Available packages: 44-pin 400 mil SOJ and  
Type II TSOP  
PIN CONFIGURATION  
BLOCK DIAGRAM  
V
DD  
V
SS  
A0  
.
.
1
2
3
4
5
6
44  
A15  
A0  
A1  
A2  
A3  
A4  
A14  
A13  
43  
42  
DECODER  
CORE  
ARRAY  
A15  
41  
40  
#OE  
#UB  
#LB  
#UB  
#CS  
#OE  
#WE  
#LB  
39  
38  
37  
36  
35  
34  
33  
32  
31  
#CS  
I/O1  
I/O2  
I/O1  
I/O16  
I/O15  
I/O14  
I/O13  
VSS  
7
8
CONTROL  
.
.
DATA I/O  
I/O16  
9
I/O3  
I/O4  
10  
11  
12  
13  
VDD  
VSS  
PIN DESCRIPTION  
VDD  
SYMBOL  
DESCRIPTION  
I/O12  
I/O11  
I/O10  
I/O9  
I/O5  
14  
15  
16  
Address Inputs  
I/O6  
I/O7  
I/O8  
#WE  
A5  
A0- A15  
I/O1- I/O16  
#CS  
30  
29  
28  
Data Inputs/Outputs  
Chip Select Inputs  
Write Enable Input  
Output Enable Input  
Lower Byte Select I/O1- I/O8  
Upper Byte Select I/O9- I/O16  
Power Supply  
NC  
17  
18  
19  
20  
21  
22  
#WE  
#OE  
A12  
A11  
27  
26  
A6  
#LB  
A10  
A9  
25  
24  
23  
A7  
A8  
#UB  
NC  
NC  
VDD  
VSS  
Ground  
NC  
No Connection  
Publication Release Date: May 2001  
Revision A5  
- 1 -  

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