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W26020AT-25 PDF预览

W26020AT-25

更新时间: 2024-11-09 22:14:55
品牌 Logo 应用领域
华邦 - WINBOND /
页数 文件大小 规格书
10页 127K
描述
128K X 16 High Speed CMOS Static RAM

W26020AT-25 技术参数

生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2, TSOP44,.46,32针数:44
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.81
最长访问时间:25 ns其他特性:CAN ALSO BE CONFIGURED AS 128K X 16
I/O 类型:COMMONJESD-30 代码:R-PDSO-G44
长度:18.41 mm内存密度:2097152 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
功能数量:1端子数量:44
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP44,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL电源:5 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.01 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.2 mA
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

W26020AT-25 数据手册

 浏览型号W26020AT-25的Datasheet PDF文件第2页浏览型号W26020AT-25的Datasheet PDF文件第3页浏览型号W26020AT-25的Datasheet PDF文件第4页浏览型号W26020AT-25的Datasheet PDF文件第5页浏览型号W26020AT-25的Datasheet PDF文件第6页浏览型号W26020AT-25的Datasheet PDF文件第7页 
W26020A  
128K ´ 16 HIGH-SPEED CMOS STATIC RAM  
GENERAL DESCRIPTION  
The W26020A is a high-speed, low-power CMOS static RAM organized as 131,072 ´ 16 bits that  
operates on a single 5-volt power supply. This device is manufactured using Winbond's high  
performance CMOS technology.  
The W26020A has an active low chip select, separate upper and lower byte selects, and a fast output  
enable. No clock or refreshing is required. Separate byte select controls (LB and UB ) allow  
individual bytes to be written and read. LB controls I/O1-I/O8, the lower byte. UB controls I/O9-  
I/O16, the upper byte. This device is well suited for use in high-density, high-speed system  
applications.  
FEATURES  
· High speed access time: 20/25 nS (max.)  
· Low power consumption:  
- Active: 1.5W (max.)  
· All inputs and outputs directly TTL compatible  
· Three-state outputs  
· Data byte control  
· Single +5V power supply  
· Fully static operation  
- LB (I/O1- I/O8), UB (I/O9- I/O16)  
· Available packages: 44-pin type two TSOP  
- No clock or refreshing  
PIN CONFIGURATION  
BLOCK DIAGRAM  
V
DD  
V
SS  
A0  
A1  
A2  
A3  
A4  
1
2
3
4
5
6
44  
43  
42  
A15  
A14  
A13  
A0  
.
.
DECODER  
CORE  
ARRAY  
A16  
41  
40  
OE  
UB  
UB  
CS  
I/O1  
I/O2  
39  
38  
37  
36  
35  
34  
33  
32  
31  
LB  
CS  
OE  
I/O1  
I/O16  
7
8
CONTROL  
.
.
DATA I/O  
I/O15  
I/O14  
I/O13  
WE  
LB  
I/O16  
I/O3  
I/O4  
9
10  
11  
12  
13  
V
SS  
V
DD  
PIN DESCRIPTION  
V
SS  
V
DD  
SYMBOL  
A0- A16  
I/O1- I/O16  
DESCRIPTION  
I/O5  
I/O12  
I/O11  
I/O10  
I/O9  
Address Inputs  
I/O6  
I/O7  
I/O8  
WE  
A5  
14  
15  
16  
Data Inputs/Outputs  
Chip Select Inputs  
Write Enable Input  
30  
29  
28  
CS  
WE  
OE  
LB  
NC  
17  
18  
19  
20  
21  
22  
A12  
A11  
A10  
A9  
27  
26  
25  
24  
23  
Output Enable Input  
A6  
Lower Byte Select I/O1- I/O8  
Upper Byte Select I/O9- I/O16  
A7  
UB  
A8  
A16  
NC  
VDD  
VSS  
NC  
Power Supply  
Ground  
No Connection  
Publication Release Date: July 1998  
Revision A3  
- 1 -  

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