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W26B04H-70LI PDF预览

W26B04H-70LI

更新时间: 2024-11-10 19:49:19
品牌 Logo 应用领域
华邦 - WINBOND 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
11页 223K
描述
Standard SRAM, 256KX16, 70ns, CMOS, PDSO44, TSOP2-44

W26B04H-70LI 技术参数

生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2, TSOP44,.46,32针数:44
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:70 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G44JESD-609代码:e3
长度:18.41 mm内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
功能数量:1端子数量:44
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:256KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP44,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL电源:3/3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最小待机电流:1.5 V子类别:SRAMs
最大压摆率:0.04 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

W26B04H-70LI 数据手册

 浏览型号W26B04H-70LI的Datasheet PDF文件第2页浏览型号W26B04H-70LI的Datasheet PDF文件第3页浏览型号W26B04H-70LI的Datasheet PDF文件第4页浏览型号W26B04H-70LI的Datasheet PDF文件第5页浏览型号W26B04H-70LI的Datasheet PDF文件第6页浏览型号W26B04H-70LI的Datasheet PDF文件第7页 
W26B04  
´ 16 CMOS STATIC RAM  
256K  
GENERAL DESCRIPTION  
The W26B04 is a normal speed, very low-power CMOS static RAM organized as 262144  
´
16 bits  
that operates on a wide voltage range from 2.7V to 3.6V power supply. The W26B04, W26B04-LE and  
W26B04-LI, can meet the requirement of various operating temperature. This device is manufactured  
using Winbond’ s high performance CMOS technology.  
FEATURES  
· Low power consumption  
· Access time: 70 nS  
· 2.7V to 3.6V supply voltage  
· Fully static operation  
· All inputs and outputs directly TTL compatible  
· Three-state outputs  
· Battery back-up operation capability  
· Data retention voltage: 1.5V (min.)  
· Data byte control  
-
#LB (I/O1- I/O8), #UB (I/O9 - I/O16)  
· Available packages: 44-pin type two TSOP,  
and TFBGA  
PIN CONFIGURATIONS  
BLOCK DIAGRAM  
PRECHARGE CKT.  
CLK GEN.  
A4  
A3  
A4  
A3  
A2  
A1  
A0  
#CS  
I/O1  
I/O2  
I/O3  
1
2
3
4
A5  
A6  
A
44  
43  
A15  
R
O
W
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
A14  
A16  
CORE CELL ARRAY  
1024 ROWS  
#OE  
D
E
C
O
D
E
R
5
6
#UB  
#LB  
I/O1  
A1  
A2  
256 X 16 COLUMNS  
7
8
A17  
A0  
6
I/O1  
5
I/O1  
9
A13  
4
I/O4  
I/O1  
10  
11  
12  
I/O1  
:
I/O16  
I/O CKT.  
COLUMN DECODER  
DATA  
CNTRL.  
3
VSS  
VDD  
SS  
V
VDD  
CLK  
GEN.  
I/O5  
I/O6  
13  
14  
15  
16  
I/O1  
44-pin  
TSOP  
A7 A6 A5  
A9 A10 A11 A12  
A8  
2
#WE  
I/O1  
1
I/O7  
I/O8  
#WE  
A17  
A16  
A15  
I/O1  
#CS  
#UB  
0
I/O  
#LB  
#OE  
17  
18  
19  
NC  
A8  
A9  
A10  
A11  
20  
21  
22  
A14  
A13  
A12  
PIN DESCRIPTION  
SYMBOL  
DESCRIPTION  
48-pin TFBGA TOP VIEW  
Address Inputs  
Data Inputs/Outputs  
A0 - A17  
I/O1 - I/O16  
#CS  
1
2
3
4
5
6
NC  
Chip Select Input  
Write Enable Input  
Lower byte select  
Upper byte select  
Output Enable Input  
Power Supply  
A
#LB  
I/O9  
I/O10  
VSS  
VDD  
#OE  
#UB  
I/O11  
I/O12  
I/O13  
A0  
A3  
A5  
A17  
NC  
A14  
A1  
A4  
A6  
A2  
#WE  
B
C
D
E
F
G
H
I/O1  
I/O3  
VDD  
#CS  
I/O2  
I/O4  
I/O5  
I/O6  
#WE  
#LB  
A7  
A16  
#UB  
SS  
V
#OE  
I/O15  
I/O7  
I/O8  
I/O14  
NC  
A15  
A13  
A10  
I/O16  
NC  
A12  
A9  
VDD  
NC  
A8  
A11  
VSS  
Ground  
NC  
No Connection  
Publication Release Date: April 2, 2002  
Revision A4  
- 1 -  

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