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W26L04AJ-12I PDF预览

W26L04AJ-12I

更新时间: 2024-11-10 18:04:39
品牌 Logo 应用领域
华邦 - WINBOND 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
10页 144K
描述
Standard SRAM, 256KX16, 12ns, CMOS, PDSO44, 0.400 INCH, SOJ-44

W26L04AJ-12I 技术参数

生命周期:Obsolete零件包装代码:SOJ
包装说明:SOJ,针数:44
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:12 nsJESD-30 代码:R-PDSO-J44
长度:28.58 mm内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
功能数量:1端子数量:44
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:256KX16
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:3.759 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
宽度:10.16 mmBase Number Matches:1

W26L04AJ-12I 数据手册

 浏览型号W26L04AJ-12I的Datasheet PDF文件第2页浏览型号W26L04AJ-12I的Datasheet PDF文件第3页浏览型号W26L04AJ-12I的Datasheet PDF文件第4页浏览型号W26L04AJ-12I的Datasheet PDF文件第5页浏览型号W26L04AJ-12I的Datasheet PDF文件第6页浏览型号W26L04AJ-12I的Datasheet PDF文件第7页 
Preliminary W26L04A  
256K ´ 16 HIGH-SPEED CMOS STATIC RAM  
GENERAL DESCRIPTION  
´
The W26L04A is a high-speed, low-power CMOS static RAM organized as 262,144 16 bits that  
operates on a single 3.3-volt power supply.  
The W26L04A has an active low chip select, separate upper and lower byte selects, and a fast output  
LB  
UB  
) allow  
enable. No clock or refreshing is required. Separate byte select controls (  
and  
LB  
individual bytes to be written and read.  
controls I/O1-I/O8, the lower byte. UB controls  
-
I/O9 I/O16, the upper byte. This device is well suited for use in high-density, high-speed system  
applications.  
FEATURES  
· High speed access time: 10/12 nS (max.)  
· Low power consumption:  
· All inputs and outputs directly TTL compatible  
· Three-state outputs  
-
Active: 660 mW (max.)  
· Data byte control  
+
· Single 3.3V power supply  
· Fully static operation  
- No clock or refreshing  
· Industrial operating temperature grade  
available  
- LB  
-
UB  
-
(I/O9 I/O16)  
(I/O1 I/O8),  
· Available packages: 44-pin 400 mil SOJ and  
44-pin TSOP(II)  
PIN CONFIGURATION  
BLOCK DIAGRAM  
VDD  
V
SS  
A0  
.
.
DECODER  
CORE  
ARRAY  
A0  
A1  
A2  
A3  
A4  
1
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
A17  
A16  
A15  
OE  
A17  
2
3
4
UB  
5
UB  
CS  
OE  
WE  
LB  
I/O1  
.
.
CONTROL  
6
LB  
CS  
I/O1  
I/O2  
I/O3  
I/O4  
DATA I/O  
7
I/O16  
I/O15  
I/O14  
I/O13  
VSS  
I/O16  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
PIN DESCRIPTION  
V
DD  
44-PIN  
V
DD  
V
SS  
SYMBOL  
DESCRIPTION  
I/O12  
I/O11  
I/O10  
I/O9  
NC  
I/O5  
I/O6  
I/O7  
I/O8  
Address Inputs  
-
A0 A17  
Data Inputs/Outputs  
Chip Select Input  
Write Enable Input  
-
I/O1 I/O16  
CS  
WE  
OE  
LB  
WE  
A5  
A14  
A13  
A12  
A11  
A10  
A6  
Output Enable Input  
A7  
A8  
A9  
Lower Byte Select I/O1- I/O8  
-
Upper Byte Select I/O9 I/O16  
UB  
DD  
V
Power Supply  
Ground  
SS  
V
NC  
No Connection  
Publication Release Date: October 1999  
Revision A1  
- 1 -  

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