Datasheet > W144_04

W144_04

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
14页	159K
描述
440BX AGPset Spread Spectrum Frequency Synthesizer

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W144_04 数据手册

W144

440BX AGPset Spread Spectrum Frequency Synthesizer

Features

Table 1. Pin Selectable Frequency

Input Address

FS3 FS2 FS1 FS0

• Maximized electromagnetic interference (EMI)

suppression using Cypress’ Spread Spectrum

technology

• Single chip system frequency synthesizer for Intel^®

440BX AGPset

CPU_F, CPU1

(MHz)

PCI_F, 1:5 (MHz)

33.4 (CPU/4)

31 (CPU/4)

37.5 (CPU/4)

35 (CPU/4)

133.6

124

150

140

105

110

• Two copies of CPU output

• Six copies of PCI output 1

• One 48-MHz output for USB

• One 24-MHz output for SIO

• Two buffered reference outputs

• One IOAPIC output

35 (CPU/3)

36.7 (CPU/3)

38.3 (CPU/3)

40 (CPU/3)

115

120

100.2

133.3

112

103

66.8

83.3

33.4 (CPU/3)

44.43 (CPU/3)

37.3 (CPU/3)

34.3 (CPU/3)

33.4 (CPU/2)

41.7 (CPU/2)

37.5 (CPU/2)

41.3 (CPU/3)

• Thirteen SDRAM outputs provide support for three

DIMMs

• Supports frequencies up to 150 MHz

• I²C interface for programming

• Power management control inputs

124

Pin Configuration^[1]

Logic Block Diagram

VDDQ3

REF0/(PCI_STOP#)

GND

VDDQ2

REF0/(PCI_STOP#)

REF1/FS2

IOAPIC

REF1/FS2*

GND

CPU_F

CPU1

VDDQ2

CLK_STOP#

SDRAM_F

GND

SDRAM0

SDRAM1

VDDQ3

SDRAM2

SDRAM3

GND

SDRAM4

SDRAM5

VDDQ3

XTAL

OSC

PLL Ref Freq

VDDQ2

IOAPIC

VDDQ3

PCI_F/MODE

**PCI1/FS3

GND

Stop

Clock

I/O Pin

Control

PCI2

PCI3

PCI4

CLK_STOP#

VDDQ2

Stop

Clock

Control

CPU1

PCI5

PLL 1

÷2,3,4

VDDQ3

SDRAMIN

GND

CPU_F

VDDQ3

PCI_F/MODE

PCI1/FS3

PCI2

SDRAM11

SDRAM10

VDDQ3

SDRAM9

SDRAM8

GND

Stop

Clock

SDRAM6

SDRAM7

VDDQ3

48MHz/FS0*

24MHz/FS1*

PCI3

Control

PCI4

PCI5

SDATA

I C

{

SDATA

SCLK

I C

Logic

SCLK

VDDQ3

48MHz/FS0

PLL2

÷2

24MHz/FS1

VDDQ3

Stop

Clock

Control

SDRAMIN

SDRAM0:11

SDRAM_F

Note:

1. * Has an internal pull-up resistors. It should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping

while ** has an internal pull down resistor.

Cypress Semiconductor Corporation

Document #: 38-07153 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised January 16, 2004

12 3 4 5 6 7...14

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