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W149

更新时间: 2024-11-05 03:18:07
品牌 Logo 应用领域
SPECTRALINEAR /
页数 文件大小 规格书
15页 202K
描述
440BX AGPset Spread Spectrum Frequency Synthesizer

W149 数据手册

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W149  
W149  
440BX AGPset Spread Spectrum Frequency Synthesizer  
PCI to PCI Output Skew:.............................................500 ps  
Features  
V
DDQ3:..................................................................... 3.3V 5%  
DDQ2:..................................................................... 2.5V 5%  
• Maximized EMI suppression using Cypress’s Spread  
Spectrum Technology  
V
• Single chip system frequency synthesizer for Intel®  
440BX AGPset  
SDRAMIN to SDRAM0:12 Delay:..........................3.7 ns typ.  
Table 1. Mode Input Table[1]  
• Two copies of CPU output  
Mode  
Pin 2  
PCI_STOP#  
REF0  
• Six copies of PCI output  
0
1
• One 48 MHz output for USB  
• One 24 MHz output for SIO  
Table 2. Pin Selectable Frequency  
• Two buffered reference outputs  
• One IOAPIC output  
Input Address  
CPU0:1  
PCI_F, 1:5  
(MHz)  
FS2 FS1 FS0  
(MHz)  
Spread%  
• Thirteen SDRAM outputs provide support for 3 DIMMs  
• Spread Spectrum feature always enabled  
• SMBus interface for programming  
• Power management control inputs  
• Smooth CPU frequency switching from 66.8–124 MHz  
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
100  
33.3 (CPU/3)  
(Reserved)  
–0.5  
100  
103  
66.8  
83.3  
66.8  
124  
33.3 (CPU/3)  
34.3 (CPU/3)  
33.4 (CPU/2)  
41.7 (CPU/2)  
33.4 (CPU/2)  
41.3 (CPU/3)  
0.5  
–0.5  
–0.5  
–0.5  
0.5  
Key Specifications  
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps  
CPU to CPU Output Skew: ........................................ 175 ps  
–0.5  
[2]  
Logic Block Diagram  
Pin Configuration  
VDDQ3  
VDDQ3  
REF0/(PCI_STOP#)  
GND  
48  
VDDQ2  
IOAPIC  
REF1/FS2*  
GND  
CPU0  
CPU1  
VDDQ2  
OE  
SDRAM12  
GND  
SDRAM0  
SDRAM1  
VDDQ3  
SDRAM2  
SDRAM3  
GND  
SDRAM4  
SDRAM5  
VDDQ3  
SDRAM6  
SDRAM7  
VDDQ3  
48MHz/FS0*  
24MHz/FS1*  
1
2
3
4
5
6
7
8
REF0/(PCI_STOP#)  
REF1/FS2  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
X1  
X2  
XTAL  
OSC  
X1  
X2  
PLL Ref Freq  
VDDQ2  
IOAPIC  
VDDQ3  
PCI_F/MODE  
PCI1  
I/O Pin  
Control  
GND  
PCI2  
PCI3  
PCI4  
PCI5  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
VDDQ2  
CPU0  
CPU1  
VDDQ3  
SDRAMIN  
GND  
SDRAM11  
SDRAM10  
VDDQ3  
SDRAM9  
SDRAM8  
GND  
PLL 1  
÷2/÷3  
VDDQ3  
PCI_F/MODE  
PCI1  
PCI2  
Stop  
Clock  
Control  
PCI3  
SDATA  
{
SCLK  
SMBus  
PCI4  
PCI5  
SDATA  
SCLK  
SMBus  
Logic  
VDDQ3  
48MHz/FS0  
PLL2  
÷2  
24MHz/FS1  
VDDQ3  
SDRAM0:12  
SDRAMIN  
13  
Notes:  
1. Mode input latched at power-up.  
2. Internal pull up resistors(*) should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping.  
Rev 1.0, November 21, 2006  
Page 1 of 15  
2200 Laurelwood Road, Santa Clara, CA 95054  
Tel:(408) 855-0555 Fax:(408) 855-0550  
www.SpectraLinear.com  

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