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W144_04

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
14页 159K
描述
440BX AGPset Spread Spectrum Frequency Synthesizer

W144_04 数据手册

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W144  
Operation  
Serial Data Interface  
Data is written to the W144 in eleven bytes of eight bits each.  
Bytes are written in the order shown in Table 4.  
The W144 features a two-pin, serial data interface that can be  
used to configure internal register settings that control  
particular device functions. Upon power-up, the W144  
initializes with default register settings, therefore the use of this  
serial data interface is optional. The serial interface is  
write-only (to the clock chip) and is the dedicated function of  
device pins SDATA and SCLOCK. In motherboard applica-  
tions, SDATA and SCLOCK are typically driven by two logic  
outputs of the chipset. Clock device register changes are  
normally made upon system initialization, if any are required.  
The interface can also be used during system operation for  
power management functions. Table 3 summarizes the control  
functions of the serial data interface.  
Table 3. Serial Data Interface Control Functions Summary  
Control Function  
Description  
Common Application  
Clock Output Disable  
Any individual clock output(s) can be disabled.  
Disabled outputs are actively held LOW.  
Unused outputs are disabled to reduce EMI  
andsystem power. Examples are clock outputs  
to unused PCI slots.  
CPU Clock Frequency  
Selection  
Provides CPU/PCI frequency selections through  
software. Frequency is changed in a smooth and  
controlled fashion.  
For alternate microprocessors and power  
management options. Smooth frequency  
transition allows CPU frequency change under  
normal system operation.  
Spread Spectrum  
Enabling  
Enables or disables spread spectrum clocking.  
For EMI reduction.  
Output Three-state  
(Reserved)  
Puts clock output into a high-impedance state.  
Production PCB testing.  
Reserved function for future device revision or  
production device testing.  
No user application. Register bit must be  
written as 0.  
Table 4. Byte Writing Sequence  
Byte  
Sequence  
Byte Name  
Bit Sequence  
Byte Description  
1
Slave Address  
11010010  
Commands the W144 to accept the bits in Data Bytes 0–6 for internal  
register configuration. Since other devices may exist on the same  
common serial data bus, it is necessary to have a specific slave address  
for each potential receiver. The slave receiver address for the W144 is  
11010010. Register setting will not be made if the Slave Address is not  
correct (or is for an alternate slave receiver).  
2
3
Command Code  
Byte Count  
Don’t Care  
Don’t Care  
Unused by the W144, therefore bit values are ignored (“don’t care”). This  
byte must be included in the data write sequence to maintain proper byte  
allocation. The Command Code Byte is part of the standard serial  
communication protocol and may be used when writing to another  
addressed slave receiver on the serial data bus.  
Unused by the W144, therefore bit values are ignored (“don’t care”). This  
byte must be included in the data write sequence to maintain proper byte  
allocation. The Byte Count Byte is part of the standard serial communi-  
cation protocolandmay be used whenwritingto anotheraddressed slave  
receiver on the serial data bus.  
Document #: 38-07153 Rev. *B  
Page 5 of 14  

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