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W147GH PDF预览

W147GH

更新时间: 2024-11-05 13:15:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 143K
描述
Processor Specific Clock Generator, CMOS, PDSO56, 0.300 INCH, SSOP-56

W147GH 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:0.300 INCH, SSOP-56
针数:56Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.9其他特性:ALSO REQUIRES 2.5V SUPPLY
JESD-30 代码:R-PDSO-G56JESD-609代码:e0
长度:18.415 mm湿度敏感等级:1
端子数量:56最高工作温度:70 °C
最低工作温度:最大输出时钟频率:100 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP56,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):220
电源:2.5,3.3 V主时钟/晶体标称频率:14.318 MHz
认证状态:Not Qualified座面最大高度:2.794 mm
子类别:Clock Generators最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

W147GH 数据手册

 浏览型号W147GH的Datasheet PDF文件第2页浏览型号W147GH的Datasheet PDF文件第3页浏览型号W147GH的Datasheet PDF文件第4页浏览型号W147GH的Datasheet PDF文件第5页浏览型号W147GH的Datasheet PDF文件第6页浏览型号W147GH的Datasheet PDF文件第7页 
PRELIMINARY  
W147G  
Frequency Generator for Integrated Core Logic  
Features  
Key Specifications  
• Maximized EMI suppression using Cypress’s Spread  
Spectrum Technology  
• Low jitter and tightly controlled clock skew  
• Highly integrated device providing clocks required for  
CPU, core logic, and SDRAM  
• Three copies of CPU clock at 66/100 MHz  
• Nine copies of 100-MHz SDRAM clocks  
• Eight copies of PCI clock  
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ..............250 ps  
APIC, 48MHz, 3V66, PCI Outputs  
Cycle-to-Cycle Jitter: ...................................................500 ps  
APIC, 48MHz, SDRAM Output Skew: .........................250 ps  
CPU, 3V66 Output Skew: ............................................175 ps  
PCI Output Skew:........................................................500 ps  
CPU to SDRAM Skew (@ 100 MHz):.................4.5 to 5.5 ns  
CPU to 3V66 Skew (@ 66 MHz): .......................7.0 to 8.0 ns  
3V66 to PCI Skew (3V66 lead):..........................1.5 to 3.5 ns  
PCI to APIC Skew: .....................................................±0.5 ns  
• Two copies of synchronous APIC clock  
• Two copies of 48-MHz clock (non-spread spectrum) op-  
timized for USB reference input and video dot clock  
• Two copies of 66-MHz fixed clock  
• One copy of 14.31818-MHz reference clock  
• Power-down control  
Table 1. Pin Selectable Functions  
2
SEL1  
SEL0  
Function  
Three-state  
Test  
• I C interface for turning off unused clocks  
0
0
1
1
0
1
0
1
66-MHz CPU  
100-MHz CPU  
Block Diagram  
Pin Configuration  
VDDQ3  
REF/APICDIV  
VDDQ3  
X1  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
GND  
1
APIC0  
2
REF/APICDIV  
3
APIC1  
VDDQ2  
CPU0  
VDDQ2  
CPU1  
CPU2_ITP  
GND  
GND  
SDRAM0  
SDRAM1  
VDDQ3  
SDRAM2  
SDRAM3  
GND  
SDRAM4  
SDRAM5  
VDDQ3  
SDRAM6  
SDRAM7  
GND  
DCLK  
VDDQ3  
PWRDWN#  
SCLK  
SDATA  
SEL1  
X1  
X2  
XTAL  
OSC  
X2  
4
GND  
GND  
PLL REF FREQ  
5
6
VDDQ2  
CPU0:1  
3V66_0  
3V66_1  
VDDQ3  
VDDQ3  
PCI0_ICH  
PCI1  
7
Divider,  
Delay,  
and  
Phase  
Control  
Logic  
8
I2C  
Logic  
2
SDATA  
SCLK  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
CPU2_ITP  
APIC0:1  
2
PCI2  
GND  
VDDQ3  
PCI3  
PLL 1  
3V66_0:1  
SEL0:1  
PCI4  
2
GND  
PCI5  
PCI0_ICH  
PCI1:7  
PCI6  
PCI7  
VDDQ3  
VDD3  
GND  
GND  
USB  
DOT  
VDDQ3  
SEL0  
36  
35  
34  
33  
32  
31  
30  
29  
7
DCLK  
25  
26  
27  
28  
PWRDWN#  
SDRAM0:7  
8
VDDQ3  
USB  
PLL2  
DOT  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
October 13, 1999, rev. **  

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