PRELIMINARY
W150
440BX AGPset Spread Spectrum Frequency Synthesizer
Features
Table 1. Mode Input Table
Mode
Pin 3
PCI_STOP#
REF0
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Single chip system frequency synthesizer for Intel
440BX AGPset
0
1
®
Table 2. Pin Selectable Frequency
Input Address
• Three copies of CPU output
• Seven copies of PCI output
• One 48-MHz output for USB / One 24-MHz for SIO
• Two buffered reference outputs
• Two IOAPIC outputs
CPU_F, 1:2
PCI_F, 0:5
FS3 FS2 FS1 FS0
(MHz)
133.3
124
150
140
105
110
115
120
100
133.3
112
103
66.8
83.3
75
(MHz)
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
33.3 (CPU/4)
31 (CPU/4)
• 17 SDRAM outputs provide support for 4 DIMMs
• Supports frequencies up to 150 MHz
37.5 (CPU/4)
35 (CPU/4)
2
• I C™ interface for programming
35 (CPU/3)
• Power management control inputs
36.7 (CPU/3)
38.3 (CPU/3)
40 (CPU/3)
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
SDRAMIN to SDRAM0:15 Delay: ..........................3.7 ns typ.
33.3 (CPU/3)
44.43 (CPU/3)
37.3 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.7 (CPU/2)
37.5 (CPU/2)
41.3 (CPU/3)
V
V
: .................................................................... 3.3V±5%
: .................................................................... 2.5V±5%
DDQ3
DDQ2
SDRAM0:15 (leads) to SDRAM_F Skew: ..............0.4 ns typ.
124
Pin Configuration[1]
Logic Block Diagram
VDDQ3
REF0/(PCI_STOP#)
VDDQ3
REF1/FS2
REF0/(PCI_STOP#)
GND
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
VDDQ2
IOAPIC0
IOAPIC_F
GND
2
REF1/FS2
X1
X2
XTAL
OSC
3
4
PLL Ref Freq
X1
5
CPU_F
VDDQ2
X2
6
7
8
9
CPU1
Stop
Clock
Control
IOAPIC_F
VDDQ3
PCI_F/MODE
PCI0/FS3
GND
VDDQ2
CPU2
I/O Pin
Control
IOAPIC0
GND
CLK_STOP#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CLK_STOP#
SDRAM_F
VDDQ3
SDRAM0
SDRAM1
GND
VDDQ2
CPU_F
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
Stop
Clock
CPU1
CPU2
Control
PLL 1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
÷2,3,4
SDRAMIN
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
VDDQ3
PCI_F/MODE
PCI0/FS3
PCI1
Stop
Clock
Control
PCI2
34
33
32
31
30
29
GND
SDRAM15
SDRAM12
SDRAM13
VDDQ3
PCI3
PCI4
25
26
27
28
SDRAM14
2
I C
Logic
SDATA
SCLK
GND
24MHz/FS0
48MHz/FS1
SDATA
SCLK
PCI5
VDDQ3
48MHz/FS1
PLL2
24MHz/FS0
VDDQ3
SDRAM0:15
Stop
Clock
SDRAMIN
Control
16
SDRAM_F
Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Corporation.
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping.
Unlike other I/O pins, input FS3 has an internal pull-down resistor.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
February 10, 2000, rev. *A