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W150_03

更新时间： 2024-09-17 03:18:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
15页 170K
描述
440BX AGPset Spread Spectrum Frequency Synthesizer

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W150_03 数据手册

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W150  
PRELIMINARY  
440BX AGPset Spread Spectrum  
Frequency Synthesizer  
Features  
Table 1. Mode Input Table  
Mode  
Pin 3  
PCI_STOP#  
REF0  
• Maximized electromagnetic interference (EMI)  
suppression using Cypress’s Spread Spectrum  
technology  
0
1
• Single-chip system frequency synthesizer for Intel®  
Table 2. Pin Selectable Frequency  
Input Address  
440BX AGPset  
• Three copies of CPU output  
• Seven copies of PCI output  
• One 48-MHz output for USB/one 24-MHz for SIO  
• Two buffered reference outputs  
• Two IOAPIC outputs  
• 17 SDRAM outputs provide support for four DIMMs  
• Supports frequencies up to 150 MHz  
• SMBus interface for programming  
• Power management control inputs  
CPU_F, 1:2  
PCI_F, 0:5  
FS3 FS2 FS1 FS0  
(MHz)  
133.3  
124  
150  
140  
105  
110  
(MHz)  
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
33.3 (CPU/4)  
31 (CPU/4)  
37.5 (CPU/4)  
35 (CPU/4)  
35 (CPU/3)  
36.7 (CPU/3)  
38.3 (CPU/3)  
40 (CPU/3)  
115  
Key Specifications  
120  
100  
133.3  
112  
CPU Cycle-to-Cycle Jitter: ..........................................250 ps  
CPU to CPU Output Skew: .........................................175 ps  
PCI to PCI Output Skew:.............................................500 ps  
SDRAMIN to SDRAM0:15 Delay:.......................... 3.7 ns typ.  
VDDQ3:..................................................................... 3.3V±5%  
VDDQ2:..................................................................... 2.5V±5%  
SDRAM0:15 (leads) to SDRAM_F Skew: ............. 0.4 ns typ.  
33.3 (CPU/3)  
44.43 (CPU/3)  
37.3 (CPU/3)  
34.3 (CPU/3)  
33.4 (CPU/2)  
41.7 (CPU/2)  
37.5 (CPU/2)  
41.3 (CPU/3)  
103  
66.8  
83.3  
75  
124  
[1]  
Logic Block Diagram  
Pin Configuration  
VDDQ3  
REF0/(PCI_STOP#)  
VDDQ3  
REF1/FS2  
REF0/(PCI_STOP#)  
GND  
1
56  
55  
54  
53  
52  
VDDQ2  
2
IOAPIC0  
IOAPIC_F  
GND  
REF1/FS2  
X1  
X2  
XTAL  
OSC  
3
4
PLL Ref Freq  
X1  
5
CPU_F  
CPU1  
VDDQ2  
CPU2  
GND  
VDDQ2  
X2  
6
7
8
9
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
Stop  
Clock  
Control  
IOAPIC_F  
VDDQ3  
PCI_F/MODE  
PCI0/FS3  
GND  
I/O Pin  
Control  
IOAPIC0  
CLK_STOP#  
SDRAM_F  
VDDQ3  
SDRAM0  
SDRAM1  
GND  
SDRAM2  
SDRAM3  
SDRAM4  
SDRAM5  
VDDQ3  
SDRAM6  
SDRAM7  
GND  
CLK_STOP#  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
VDDQ2  
CPU_F  
PCI1  
PCI2  
Stop  
Clock  
PCI3  
CPU1  
CPU2  
PCI4  
Control  
PLL 1  
VDDQ3  
PCI5  
÷2,3,4  
SDRAMIN  
SDRAM11  
SDRAM10  
VDDQ3  
SDRAM9  
SDRAM8  
GND  
VDDQ3  
PCI_F/MODE  
PCI0/FS3  
PCI1  
Stop  
Clock  
Control  
PCI2  
SDRAM15  
SDRAM12  
SDRAM13  
VDDQ3  
24MHz/FS0  
48MHz/FS1  
PCI3  
PCI4  
25  
26  
27  
28  
SDRAM14  
SDATA  
SCLK  
SMBus  
Logic  
GND  
SDATA  
SCLK  
PCI5  
VDDQ3  
Note:  
48MHz/FS1  
PLL2  
1. 1.Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function  
with parentheses determined by MODE pin resistor strapping. Unlike other I/O pins, input  
FS3 has an internal pull-down resistor.  
24MHz/FS0  
VDDQ3  
SDRAM0:15  
Stop  
Clock  
Control  
SDRAMIN  
16  
SDRAM_F  
Cypress Semiconductor Corporation  
Document #: 38-07177 Rev. *B  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised January 27, 2003  
1234567...15

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