W149
440BX AGPset Spread Spectrum Frequency Synthesizer
V
:.....................................................................3.3V±5%
Features
DDQ3
V
:.....................................................................2.5V±5%
DDQ2
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Single chip system frequency synthesizer for Intel
440BX AGPset
• Two copies of CPU output
• Six copies of PCI output
• One 48-MHz output for USB
SDRAMIN to SDRAM0:12 Delay:.......................... 3.7 ns typ.
®
[1]
Table 1. Mode Input Table
Mode
Pin 2
PCI_STOP#
REF0
0
1
• One 24-MHz output for SIO
• Two buffered reference outputs
• One IOAPIC output
• Thirteen SDRAM outputs provide support for 3 DIMMs
• Spread Spectrum feature always enabled
• SMBus interface for programming
• Power management control inputs
• Smooth CPU frequency switching from 66.8–124 MHz
Table 2. Pin Selectable Frequency
Input Address
CPU0:1
(MHz)
PCI_F, 1:5
(MHz)
Spread
%
FS2 FS1 FS0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
100
33.3 (CPU/3)
(Reserved)
–0.5
100
103
66.8
83.3
66.8
124
33.3 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.7 (CPU/2)
33.4 (CPU/2)
41.3 (CPU/3)
±0.5
–0.5
–0.5
–0.5
±0.5
–0.5
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
Pin Configuration[2]
Logic Block Diagram
VDDQ3
VDDQ3
REF0/(PCI_STOP#)
GND
48
VDDQ2
IOAPIC
REF1/FS2*
GND
CPU0
CPU1
VDDQ2
OE
SDRAM12
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
VDDQ3
48MHz/FS0*
24MHz/FS1*
1
REF0/(PCI_STOP#)
REF1/FS2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2
3
X1
X2
XTAL
OSC
X1
4
PLL Ref Freq
X2
5
VDDQ3
PCI_F/MODE
PCI1
6
VDDQ2
IOAPIC
7
I/O Pin
Control
8
GND
PCI2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PCI3
PCI4
VDDQ2
PCI5
VDDQ3
SDRAMIN
GND
CPU0
CPU1
PLL 1
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
÷2/÷3
VDDQ3
PCI_F/MODE
PCI1
PCI2
SDATA
SCLK
Stop
Clock
SMBus
{
PCI3
PCI4
Control
PCI5
SDATA
SCLK
SMBus
Logic
VDDQ3
48MHz/FS0
PLL2
÷2
24MHz/FS1
VDDQ3
SDRAM0:12
SDRAMIN
13
Intel is a registered trademark of Intel Corporation.
Notes:
1. Mode input latched at power-up.
2. Internal pull up resistors(*) should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
November 16, 2000, rev. *B