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VSC837VN PDF预览

VSC837VN

更新时间: 2024-10-28 13:15:31
品牌 Logo 应用领域
VITESSE 开关
页数 文件大小 规格书
26页 342K
描述
Crossbar Switch, CMOS, PBGA480, 37.50 X 37.50 MM, TBGA-480

VSC837VN 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:BGA,针数:480
Reach Compliance Code:compliant风险等级:5.71
边界扫描:NOJESD-30 代码:S-PBGA-B480
长度:37.5 mm低功率模式:YES
端子数量:480最高工作温度:85 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY认证状态:Not Qualified
座面最大高度:1.925 mm最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
宽度:37.5 mmuPs/uCs/外围集成电路类型:DSP PERIPHERAL, CROSSBAR SWITCH
Base Number Matches:1

VSC837VN 数据手册

 浏览型号VSC837VN的Datasheet PDF文件第2页浏览型号VSC837VN的Datasheet PDF文件第3页浏览型号VSC837VN的Datasheet PDF文件第4页浏览型号VSC837VN的Datasheet PDF文件第6页浏览型号VSC837VN的Datasheet PDF文件第7页浏览型号VSC837VN的Datasheet PDF文件第8页 
VITESSE  
SEMICONDUCTOR CORPORATION  
Preliminary Data Sheet  
3.2Gb/s  
68x68 Crosspoint Switch  
VSC837  
AC Characteristics  
Table 1: Data Path  
Symbol  
Parameter  
Min Typ Max Units  
fRATE  
tSKW  
tPDAY  
tR, tF  
tR, tF  
tJR  
Maximum Data Rate  
300  
750  
3.2  
Gb/s  
ps  
Channel-to-channel delay skew  
Propagation Delay from an A input to a Y output  
High-speed input rise/fall times, 20% to 80%  
High-speed output rise/fall times, 20% to 80%  
Output added delay jitter, rms(1, 2)  
ps  
150  
150  
10  
ps  
ps  
ps  
tJP  
Output added delay jitter, peak-to-peak(1, 2)  
40  
ps  
NOTES:(1) Tested on a sample basis only. (2) Broadband (unfiltered) deterministic jitter added to a jitter-free input, 223-1 PRBS data pattern.  
Table 2: Program Interface Timing  
Symbol  
Parameter  
Min Typ Max Units  
tsWRB  
thWRB  
tpwLW  
Setup time from INCHAN[6:0] or OUTCHAN[6:0] to rising edge of WRB  
Hold time from rising edge of WRB to INCHAN[6:0] or OUTCHAN[6:0]  
Pulse width (HIGH or LOW) on LOAD  
3.35  
1.45  
6.75  
ns  
ns  
ns  
Setup time from CSB to falling edge of LOAD or ALE_SCN in parallel or burst  
mode, or rising edge of LOAD in serial mode.  
tsCSB  
0
ns  
Hold time of CSB rising edge after LOAD or ALE_SCN rising in parallel or  
burst mode, or falling edge of LOAD in serial mode, or falling edge of CONFIG  
in any mode.  
thCSB  
0
ns  
tpwCFG  
tsSDIN  
Pulse width (HIGH or LOW) on CONFIG  
6.75  
1.65  
1.0  
ns  
ns  
ns  
ns  
ns  
ns  
Setup time from INCHAN0_SDIN to INCHAN1_SCLK rising  
Hold time of INCHAN0_SDIN after INCHAN1_SCLK rising  
Minimum period of SCLK in serial mode  
thSDIN  
tperSCLK  
tsLOAD  
thLOAD  
15  
Setup time from LOAD to INCHAN1_SCLK rising  
Hold time of LOAD after INCHAN1_SCLK rising  
1.85  
0.95  
Setup time from SERIAL rising to INCHAN1_SCLK rising when entering serial  
mode or SERIAL falling to LOAD falling when entering parallel mode or  
SERIAL falling to LOAD rising when entering burst mode.  
tsSERIAL  
0.90  
ns  
Hold time from INCHAN1_SCLK rising to SERIAL falling when exiting serial  
mode.  
thSERIAL  
tsBURST  
0
ns  
ns  
Setup time from BURST rising to LOAD rising when entering burst mode or  
BURST falling to LOAD falling when entering parallel mode.  
1.85  
thBURST  
tdsDOUT  
tpwINITB  
Hold time from LOAD rising to BURST falling when exiting burst mode.  
Delay from INCHAN1_SCLK rising to SDOUT, 20pF load.  
Pulse width (HIGH or LOW) on INITB  
2.45  
6.20  
ns  
ns  
ns  
6.75  
Setup time from ALE_SCN to INCHAN1_SCLK rising when starting or  
completing a serial read-back sequence.  
tsSCAN  
thSCAN  
1.65  
1.0  
ns  
ns  
Hold time of ALE_SCN after INCHAN1_SCLK rising when starting or  
completing a serial read-back sequence.  
© VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012  
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com  
Internet: www.vitesse.com  
G52309-0, Rev 3.0  
02/16/01  
Page 5  

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