VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
3.2Gb/s
68x68 Crosspoint Switch
VSC837
AC Characteristics
Table 1: Data Path
Symbol
Parameter
Min Typ Max Units
fRATE
tSKW
tPDAY
tR, tF
tR, tF
tJR
Maximum Data Rate
—
—
—
—
—
—
—
—
300
750
—
3.2
—
Gb/s
ps
Channel-to-channel delay skew
Propagation Delay from an A input to a Y output
High-speed input rise/fall times, 20% to 80%
High-speed output rise/fall times, 20% to 80%
Output added delay jitter, rms(1, 2)
—
ps
150
150
10
ps
—
ps
—
ps
tJP
Output added delay jitter, peak-to-peak(1, 2)
—
40
ps
NOTES:(1) Tested on a sample basis only. (2) Broadband (unfiltered) deterministic jitter added to a jitter-free input, 223-1 PRBS data pattern.
Table 2: Program Interface Timing
Symbol
Parameter
Min Typ Max Units
tsWRB
thWRB
tpwLW
Setup time from INCHAN[6:0] or OUTCHAN[6:0] to rising edge of WRB
Hold time from rising edge of WRB to INCHAN[6:0] or OUTCHAN[6:0]
Pulse width (HIGH or LOW) on LOAD
3.35
1.45
6.75
—
—
—
—
—
—
ns
ns
ns
Setup time from CSB to falling edge of LOAD or ALE_SCN in parallel or burst
mode, or rising edge of LOAD in serial mode.
tsCSB
0
—
—
ns
Hold time of CSB rising edge after LOAD or ALE_SCN rising in parallel or
burst mode, or falling edge of LOAD in serial mode, or falling edge of CONFIG
in any mode.
thCSB
0
—
—
ns
tpwCFG
tsSDIN
Pulse width (HIGH or LOW) on CONFIG
6.75
1.65
1.0
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Setup time from INCHAN0_SDIN to INCHAN1_SCLK rising
Hold time of INCHAN0_SDIN after INCHAN1_SCLK rising
Minimum period of SCLK in serial mode
thSDIN
tperSCLK
tsLOAD
thLOAD
15
Setup time from LOAD to INCHAN1_SCLK rising
Hold time of LOAD after INCHAN1_SCLK rising
1.85
0.95
Setup time from SERIAL rising to INCHAN1_SCLK rising when entering serial
mode or SERIAL falling to LOAD falling when entering parallel mode or
SERIAL falling to LOAD rising when entering burst mode.
tsSERIAL
0.90
—
—
ns
Hold time from INCHAN1_SCLK rising to SERIAL falling when exiting serial
mode.
thSERIAL
tsBURST
0
—
—
—
—
ns
ns
Setup time from BURST rising to LOAD rising when entering burst mode or
BURST falling to LOAD falling when entering parallel mode.
1.85
thBURST
tdsDOUT
tpwINITB
Hold time from LOAD rising to BURST falling when exiting burst mode.
Delay from INCHAN1_SCLK rising to SDOUT, 20pF load.
Pulse width (HIGH or LOW) on INITB
2.45
—
—
—
—
—
6.20
—
ns
ns
ns
6.75
Setup time from ALE_SCN to INCHAN1_SCLK rising when starting or
completing a serial read-back sequence.
tsSCAN
thSCAN
1.65
1.0
—
—
—
—
ns
ns
Hold time of ALE_SCN after INCHAN1_SCLK rising when starting or
completing a serial read-back sequence.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52309-0, Rev 3.0
02/16/01
Page 5