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VSC837VN PDF预览

VSC837VN

更新时间: 2024-10-28 13:15:31
品牌 Logo 应用领域
VITESSE 开关
页数 文件大小 规格书
26页 342K
描述
Crossbar Switch, CMOS, PBGA480, 37.50 X 37.50 MM, TBGA-480

VSC837VN 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:BGA,针数:480
Reach Compliance Code:compliant风险等级:5.71
边界扫描:NOJESD-30 代码:S-PBGA-B480
长度:37.5 mm低功率模式:YES
端子数量:480最高工作温度:85 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY认证状态:Not Qualified
座面最大高度:1.925 mm最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
宽度:37.5 mmuPs/uCs/外围集成电路类型:DSP PERIPHERAL, CROSSBAR SWITCH
Base Number Matches:1

VSC837VN 数据手册

 浏览型号VSC837VN的Datasheet PDF文件第1页浏览型号VSC837VN的Datasheet PDF文件第2页浏览型号VSC837VN的Datasheet PDF文件第4页浏览型号VSC837VN的Datasheet PDF文件第5页浏览型号VSC837VN的Datasheet PDF文件第6页浏览型号VSC837VN的Datasheet PDF文件第7页 
VITESSE  
SEMICONDUCTOR CORPORATION  
Preliminary Data Sheet  
3.2Gb/s  
68x68 Crosspoint Switch  
VSC837  
Programming Interface  
Parallel Mode  
In parallel mode (SERIAL=0, BURST=0), the binary word on INCHAN[6:0] is the numerical identifier of  
the input that will be routed to the specified output. OUTCHAN[6:0] is the numerical identifier of the output  
being programmed. A rising edge on the LOAD signal will transfer the programming data to the shadow regis-  
ter in the program memory. Raising CONFIG (asynchronously) will transfer the programming data to the main  
latches in the program memory and cause the internal select signals in the core to re-configure the multiplexer.  
Lowering CONFIG will latch the main latches. CONFIG may be tied HIGH to enable programming take effect  
instantaneously.  
This interface may be used with multiplexed address/data buses by using only INCHAN[6:0] without  
OUTCHAN[6:0] and dropping ALE when the address of the output to be programmed is present on  
INCHAN[6:0]. After the address is latched, the input address may be presented on INCHAN[6:0] and pro-  
gramming proceeds as above.  
No read-back capability is provided in parallel mode. Read-back for diagnostic purposes is provided in  
serial mode via the scan function.  
Serial Mode  
In serial mode (SERIAL=1, BURST=0), the INCHAN0 pin becomes the serial data input and the  
INCHAN1 pin becomes the serial clock (rising edge triggered). A serial word of the form [Output][Input] is  
shifted into the internal shift register, and the LOAD pin is asserted (HIGH) coincident with the last bit of the  
data word to signal that the word is to be applied. This transfers the input identifier to the shadow register of the  
addressed output. CONFIG is then applied (asynchronously) to transfer one or more program commands to the  
main latches of the program memories.  
The SDOUT pin follows the data on the INCHAN0_SDIN pin 14 clock cycles later. This enables the user  
to chain the serial ports of several crosspoints, shift program data for all switches through such a chain, and  
assert LOAD on all switches simultaneously to program all of the connections simultaneously.  
The output field is 7 bits long, representing the binary numerical identifier of the output to be programmed.  
The input field is 7 bits long, representing the numerical identifier of the input that will be routed to the speci-  
fied output.  
Serial Read-Back  
Read-back of the program memory contents is accomplished in serial mode by setting the ALE_SCN pin  
HIGH. This will serially shift out the contents of the main latches in the program memories, slice 68 first and  
slice 0 last, and MSB-first, LSB-last for each 7-bit word. One rising edge of INCHAN1_SCLK with  
ALE_SCN=0 and SERIAL=1 must occur to load the entire 483-bit shift register prior to shifting out data. At a  
clock rate of 66MHz, this operation takes 7.26µs.  
© VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012  
G52309-0, Rev 3.0  
02/16/01  
Page 3  
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com  
Internet: www.vitesse.com  

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