VSC838

更新时间： 2024-01-16 21:41:36

品牌	Logo	应用领域
VITESSE		开关
页数	文件大小	规格书
20页	298K
描述
3.2Gb/s 36x37 Crosspoint Switch

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VSC838 技术参数

生命周期：	Contact Manufacturer	包装说明：	BGA,
Reach Compliance Code：	compliant	风险等级：	5.72
边界扫描：	NO	JESD-30 代码：	S-PBGA-B480
长度：	37.5 mm	低功率模式：	YES
端子数量：	480	最高工作温度：	85 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	认证状态：	Not Qualified
座面最大高度：	1.925 mm	最大供电电压：	2.625 V
最小供电电压：	2.375 V	标称供电电压：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
宽度：	37.5 mm	uPs/uCs/外围集成电路类型：	DSP PERIPHERAL, CROSSBAR SWITCH
Base Number Matches：	1

VSC838 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

3.2Gb/s

36x37 Crosspoint Switch

VSC838

Features

• 36 Input by 37 Output Crosspoint Switch

• 66MHz Dual Programming Port

• 3.2Gb/s NRZ Data Bandwidth

• Parallel and Serial programming modes

• Programmable On-Chip I/O Termination

• Differential CML Output Drivers

• Single 2.5V Supply

• Non-Blocking Architecture Broadcast and Multicast

Capabilities

• LVTTL/2.5V CMOS Control I/O (3.3V tolerant)

• Input Signal Activity Monitoring Function

• 6W Typical—Low Drive Mode

7W Typical—High Drive Mode

• Integrated Signal Equalization (ISE) for Deterministic

Jitter Reduction

• High Performance 37.5mm, 480 TBGA Package

General Description

The VSC838 is a monolithic 36x36 asynchronous crosspoint switch, designed to carry broadband data

streams. The VSC838 also has an internal 37 output channel which is used in conjunction with the Activity

Monitor to allow in system diagnostics.

A high degree of signal integrity is maintained throughout the chip via fully differential signal paths.

The crosspoint function is based on a multiplexer array architecture. Each data output is driven by a 36:1

multiplexer that can be programmed to one and only one of its 36 inputs. The signal path is unregistered and

fully asynchronous, so there are not any restrictions on the phase, frequency, or signal pattern at each input.

Each high-speed output is a fully differential, switched current driver with switchable on-die terminations

for maximum signal integrity. Data inputs are terminated on-die through 100Ω impedance between true and

complement inputs (see Input Termination section for further details).

A dual mode programming interface is provided that allows programming commands to be sent as serial

data or parallel data. Core programming can be random for each port address, or multiple program assignments

can be queued and issued simultaneously. The programming may be initialized to a “straight-through” configu-

ration (A0 to Y0, A1 to Y1, etc.) using the INIT pin.

Unused channels may be powered down to allow efficient use of the switch in applications that require only

a subset of the channels. Power-down can be accomplished in hardware, via dedicated power pins for pairs of

input and output channels, or in software by programming individual unused outputs with a disable code.

VSC838 Block Diagram

A35

Y35

control

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

G52351-0, Rev 3.0

02/12/01

Page 1

12 3 4 5 6 7...20

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