Datasheet > VSC830QZ

VSC830QZ

更新时间： 2024-01-11 08:46:36

品牌	Logo	应用领域
VITESSE		开关
页数	文件大小	规格书
18页	185K
描述
2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch

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技术参数
数据手册

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VSC830QZ 技术参数

生命周期：	Transferred	零件包装代码：	QFP
包装说明：	QFP,	针数：	44
Reach Compliance Code：	compliant	风险等级：	5.66
边界扫描：	NO	最大时钟频率：	2.48 MHz
外部数据总线宽度：	2	JESD-30 代码：	S-PQFP-G44
长度：	10 mm	低功率模式：	YES
端子数量：	44	最高工作温度：	85 °C
最低工作温度：		输出数据总线宽度：	2
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装形状：	SQUARE	封装形式：	FLATPACK
认证状态：	Not Qualified	座面最大高度：	2 mm
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	宽度：	10 mm
uPs/uCs/外围集成电路类型：	DSP PERIPHERAL, CROSSBAR SWITCH	Base Number Matches：	1

VSC830QZ 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

2.7Gb/s Asynchronous

Dual 2x2 Crosspoint Switch

VSC830

Features

• Dual 2x2 Crosspoint Switch

• 50Ω Source Terminated Output Driver and

Programmable Input Terminations

• 2.7Gb/s NRZ Data Bandwidth, 2.7GHz Signal

Bandwidth

• Single 3.3V Supply, 1W Typical Dissipation

• Power-Down Capability for Unused Outputs

• Compact 44-Pin PQFP, 10x10mm Package

• PECL/TTL-Compatible Control Inputs

• PECL-Compatible High-Speed I/O

General Description

The VSC830 is a monolithic dual 2x2 asynchronous crosspoint switch, designed for critical signal path

control and buffering applications, such as loop-back, protection switching, and multi-channel backplane

driver/receivers. Signal path delay is tightly matched between each output channel to eliminate the need for

delay path compensation when switching between signal sources.

The crosspoint function is based on a multiplexer tree architecture. Each 2x2 switch can be considered as a

pair of 2:1 multiplexers that share the same inputs. The signal path through each switch is fully differential and

delay matched. The signal path is unregistered, so there are no restrictions on the phase, frequency, or signal

pattern at each input. Unused outputs can be independently powered off, thereby eliminating power on unused

sections (see Design Guide section in this data sheet). The switch control inputs can be configured to be com-

patible with PECL or TTL levels. The high-speed input and output levels are nominally PECL compatible and

capable of interfacing with a wide range of termination schemes.

VSC830 Symbol Diagram

S1,S2

G52192-0, Rev 4.0

05/23/01

Page 1

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

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