DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72852
IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI
The µPD72852 is a two-port physical layer LSI that complies with the IEEE1394a-2000 specifications.
The µPD72852 supports transfers of up to 400 Mbps and consumes less power than the µPD72850B. The
µPD72852 is suitable for battery systems with an IEEE1394 interface.
FEATURES
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The two-port physical layer LSI complies with IEEE1394a-2000
Fully interoperable with IEEE1394 std 1394 Link (FireWireTM, i.LINKTM
Meets IntelTM Mobile Power Guideline 2000
)
Full IEEE1394a-2000 support includes: Suspend/Resume, connection debounce, arbitrated short bus reset, multi-
speed concatenation, arbitration acceleration, fly-by concatenation
Fully compliant with OHCI requirements
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Small package: 64-pin plastic LQFP
Super low power: 68 mA (Operating mode)
: 115 µA (Suspend mode)
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Data rate: 400/200/100 Mbps
Supports PHY pinging and remote PHY access packets
3.3 V single power supply (if power not supplied via node: 3.0 V single power supply)
24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency
64-bit flexible register incorporated in PHY register
Electrically isolated Link interface
Supports LPS/Link-on as part of PHY/Link interface
External filter capacitors for PLL not required
Extended Resume signaling for compatibility with legacy DV devices
System power management by signaling of node power class information
Cable power monitor (CPS) is equipped
ORDERING INFORMATION
Part number
Package
µPD72852GB-8EU
64-pin plastic LQFP (10 x 10)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14920EJ3V0DS00 (3rd edition)
Date Published March 2001 NS CP(K)
Printed in Japan
The mark shows major revised points.
2000