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UPD72870AF1-FA2 PDF预览

UPD72870AF1-FA2

更新时间: 2024-11-24 12:16:59
品牌 Logo 应用领域
日电电子 - NEC 微控制器和处理器串行IO控制器通信控制器外围集成电路数据传输时钟
页数 文件大小 规格书
52页 326K
描述
IEEE1394 1-CHIP OHCI HOST CONTROLLER

UPD72870AF1-FA2 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:LFBGA,针数:192
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.74Is Samacsys:N
其他特性:ALSO OPERATES WITH 5V SUPPLY地址总线宽度:32
边界扫描:YES最大时钟频率:33 MHz
最大数据传输速率:50 MBps外部数据总线宽度:32
JESD-30 代码:S-PBGA-B192长度:14 mm
低功率模式:YES串行 I/O 数:1
端子数量:192最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH认证状态:Not Qualified
座面最大高度:1.46 mm最大供电电压:3.63 V
最小供电电压:2.97 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
宽度:14 mmuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches:1

UPD72870AF1-FA2 数据手册

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PRELIMINARY DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD72870A  
IEEE1394 1-CHIP OHCI HOST CONTROLLER  
The µPD72870A is the LSI which integrated OHCI-Link and PHY function into a single chip.  
The µPD72870A complies with the P1394a draft 2.0 specifications and the OpenHCI IEEE1394 1.0, and works up  
to 400 Mbps.  
It makes design so compact for PC and PC card application.  
FEATURES  
Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0  
Compliant with Physical Layer Services as defined in P1394a draft 2.0 (Data Rate 100/200/400 Mbps)  
Numbers of supported port (1, 2, 3 ports) are selectable  
Compliant with protocol enhancement as defined in P1394a draft 2.0  
Modular 32-bit host interface compliant to PCI Specification release 2.1  
Support PCI-Bus Power Management Interface Specification release 1.0  
Modular 32-bit host interface compliant to Card Bus Specification  
Cycle Master and Isochronous Resource Manager capable  
Built-in FIFOs for isochronous transmit (1024 bytes), asynchronous transmit (1024 bytes), and receive (2048  
bytes)  
32-bit CRC generation and checking for receive/transmit packets  
4 isochronous transmit DMAs and 4 isochronous receive DMAs supported  
32-bit DMA channels for physical memory read/write  
Clock generation by 24.576 MHz X’tal  
Internal control and operational registers direct-mapped to PCI configuration space  
2-wire Serial EEPROMTM interface supported  
Separate power supply Link and PHY  
Programmable latency timer from serial EEPROM in Cardbus mode (CARD_ON = 1)  
ORDERING INFORMATION  
Part number  
Package  
µPD72870AGM-8ED  
µPD72870AF1-FA2  
160-pin plastic LQFP (Fine pitch) (24 x 24)  
192-pin plastic FBGA (14 x 14)  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. S14653EJ1V0DS00 (1st edition)  
2000  
Date Published January 2000 NS CP (K)  
Printed in Japan  

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