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UPD72874 PDF预览

UPD72874

更新时间: 2024-02-05 07:40:41
品牌 Logo 应用领域
日电电子 - NEC 控制器
页数 文件大小 规格书
40页 291K
描述
IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER

UPD72874 技术参数

是否Rohs认证: 符合生命周期:Obsolete
Reach Compliance Code:compliantFactory Lead Time:1 week
风险等级:5.82JESD-30 代码:S-PQFP-G120
JESD-609代码:e6湿度敏感等级:3
端子数量:120最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:TQFP120,.64SQ,16
封装形状:SQUARE封装形式:FLATPACK
电源:3.3/5 V认证状态:Not Qualified
子类别:Bus Controllers表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Bismuth (Sn98Bi2)端子形式:GULL WING
端子节距:0.4 mm端子位置:QUAD

UPD72874 数据手册

 浏览型号UPD72874的Datasheet PDF文件第2页浏览型号UPD72874的Datasheet PDF文件第3页浏览型号UPD72874的Datasheet PDF文件第4页浏览型号UPD72874的Datasheet PDF文件第5页浏览型号UPD72874的Datasheet PDF文件第6页浏览型号UPD72874的Datasheet PDF文件第7页 
PRELIMINARY DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD72874  
IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER  
The µPD72874 is the LSI that integrated OHCI-Link and PHY function into a single chip. The µPD72874 complies  
with the 1394 OHCI Specification 1.1 and the IEEE Std 1394a-2000 specifications, and works up to 400 Mbps.  
It makes design so compact for PC and PC card application.  
FEATURES  
Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.1  
Compliant with Physical Layer Services as defined in IEEE Std 1394a-2000  
Provides three cable ports at 100/200/400 Mbps  
Super Low power consumption for Physical Layer  
Compliant with protocol enhancement as defined in IEEE Std1394a-2000  
Modular 32-bit host interface compliant to PCI Specification release 2.2  
Supports PCI-Bus Power Management Interface Specification release 1.1  
Modular 32-bit host interface compliant to Card Bus Specification  
Cycle Master and Isochronous Resource Manager capable  
Built-in FIFOs for isochronous transmit (2048 bytes), asynchronous transmit (2048 bytes), and receive (3072  
bytes)  
Supports D0, D1, D2, D3hot  
Supports wake up function from D3cold  
32-bit CRC generation and checking for receive/transmit packets  
4 isochronous transmit DMAs and 4 isochronous receive DMAs supported  
32-bit DMA channels for physical memory read/write  
Clock generation by 24.576 MHz X’tal  
2-wire Serial EEPROMTM interface supported  
Separate power supply Link and PHY  
Programmable latency timer from serial EEPROM in Cardbus mode (CARD_ON = 1)  
ORDERING INFORMATION  
Part number  
Package  
µPD72874GC-YEB  
120-pin plastic TQFP (Fine pitch) (14 x 14)  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. S15306EJ2V0DS00 (2nd edition)  
Date Published April 2002 NS CP (K)  
Printed in Japan  
The mark shows major revised points.  
2001  

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