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UPD72852AGB-8EU PDF预览

UPD72852AGB-8EU

更新时间: 2024-11-19 22:52:35
品牌 Logo 应用领域
日电电子 - NEC 微控制器和处理器串行IO控制器通信控制器外围集成电路数据传输时钟
页数 文件大小 规格书
48页 363K
描述
IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI

UPD72852AGB-8EU 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:10 X 10 MM, PLASTIC, LQFP-64Reach Compliance Code:compliant
风险等级:5.84Is Samacsys:N
地址总线宽度:2边界扫描:NO
最大时钟频率:24.576 MHz最大数据传输速率:50 MBps
外部数据总线宽度:8JESD-30 代码:S-PQFP-G64
JESD-609代码:e0长度:10 mm
低功率模式:NO串行 I/O 数:2
端子数量:64最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:MOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIALBase Number Matches:1

UPD72852AGB-8EU 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD72852A  
IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI  
The µPD72852A is a two-port physical layer LSI that complies with the IEEE1394a-2000 specifications.  
FEATURES  
The two-port physical layer LSI complies with IEEE1394a-2000  
Fully interoperable with IEEE1394 std 1394 Link (FireWireTM, i.LINKTM  
Meets IntelTM Mobile Power Guideline 2000  
Full IEEE1394a-2000 support includes: Suspend/Resume, connection debounce, arbitrated short bus reset, multi-speed  
concatenation, arbitration acceleration, fly-by concatenation  
Suspend Debounce timer for ESD  
“BIAS Detected” signal output  
Double speed signal filter for BIAS Ringing  
Small package: 64-pin plastic LQFP  
Super low power : 68 mA (Operating mode)  
)
: 115 µA (Suspend mode)  
Data rate: 400/200/100 Mbps  
Supports PHY pinging and remote PHY access packets  
3.3 V single power supply (if power not supplied via node: 3.0 V single power supply)  
24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency  
64-bit flexible register incorporated in PHY register  
Electrically isolated Link interface  
Supports LPS/Link-on as part of PHY/Link interface  
External filter capacitors for PLL not required  
Extended Resume signaling for compatibility with legacy DV devices  
System power management by signaling of node power class information  
Cable power monitor (CPS) is equipped  
ORDERING INFORMATION  
Part number  
Package  
µPD72852AGB-8EU  
64-pin plastic LQFP (10 × 10)  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
The mark shows major revised points.  
Document No.  
Date Published  
Printed in Japan  
S16725EJ2V0DS00 (2nd edition)  
March 2004 NS CP (K)  
2003  

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