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UPD46128512-E9X PDF预览

UPD46128512-E9X

更新时间： 2024-02-26 22:33:29
品牌 Logo 应用领域
日电电子 - NEC 存储内存集成电路静态存储器
页数 文件大小 规格书
82页 817K
描述
128M-BIT CMOS MOBILE SPECIFIED RAM 8M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION

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UPD46128512-E9X 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LFBGA,针数：93
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.87
最长访问时间：70 nsJESD-30 代码：R-PBGA-B93
JESD-609代码：e0长度：12 mm
内存密度：134217728 bit内存集成电路类型：STANDARD SRAM
内存宽度：16功能数量：1
端子数量：93字数：8388608 words
字数代码：8000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-30 °C
组织：8MX16封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.4 mm最大供电电压 (Vsup)：2 V
最小供电电压 (Vsup)：1.7 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：TIN LEAD端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：9 mm
Base Number Matches：1

UPD46128512-E9X 数据手册

 浏览型号UPD46128512-E9X的Datasheet PDF文件第3页浏览型号UPD46128512-E9X的Datasheet PDF文件第4页浏览型号UPD46128512-E9X的Datasheet PDF文件第5页浏览型号UPD46128512-E9X的Datasheet PDF文件第7页浏览型号UPD46128512-E9X的Datasheet PDF文件第8页浏览型号UPD46128512-E9X的Datasheet PDF文件第9页 
μ PD46128512-X  
Burst Operation  
Mode  
/CE1  
CE2  
CLK  
/ADV  
/OE  
/WE  
/LB  
/UB  
DQ  
DQ0 to DQ7 DQ8 to DQ15  
/WAIT  
Note8  
Not selected (Standby Mode 1)  
H
H
L
×
×
×
×
×
×
×
×
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Not selected (Standby Mode 2) Note1  
×
×
×
×
×
Note7  
Note7  
Note9  
Note9  
Start address latch  
L
H
L
×
×
×
×
High-Z Note5  
High-Z Note5  
×
Note4  
Note4  
Advanced burst read to next address  
H
L
H
DOUT  
DOUT  
Output  
Valid  
Burst read suspend Note2  
H
L
High-Z  
DOUT  
High-Z  
DIN  
High-Z  
DOUT  
High-Z  
DIN  
HIGH  
HIGH  
High-Z  
Output  
Valid  
Burst read resume Note2  
Burst read termination Note3  
Advanced burst write to next address  
×
×
L
H
L
Note4  
Burst write suspend Note2  
Burst write resume Note2  
Burst write termination Note3  
Abort write Note6  
H
L
×
High-Z  
DIN  
High-Z  
DIN  
HIGH  
HIGH  
High-Z  
HIGH  
×
×
High-Z  
High-Z  
High-Z  
High-Z  
L
×
Note10 HIGH HIGH  
Notes1. CE2 pin must be fixed HIGH except Standby Mode 2 (refer to 2.3 Standby Mode Status Transition).  
2. Be sure to suspend or resume a burst read after outputting the first read access data.  
Be sure to suspend or resume a burst write after latching the first write data.  
Burst write suspend or resume is available when setting WC = 1 (/WE level control) through Mode Register  
Set.  
3. /CE1 must be fixed HIGH during tTRB specification until next read or write operation.  
4. Valid clock edge shall be set either positive or negative edge through Mode Register Set.  
5. If /OE = LOW and /LB = /UB = LOW, output is valid. If /OE = LOW and /LB = /UB = HIGH, output is high  
impedance.  
If /WE = LOW, output is high impedance. If /OE = /WE = HIGH, output is high impedance.  
6. If /WE = LOW and /LB = /UB = HIGH, memory does not accept write data, so write operation is not  
available.  
7. Both of two pins (/OE and /WE) or either of two should be connected to HIGH. It is prohibited to bring the  
both /OE and /WE to LOW.  
8. Refer to the 4.10 /WAIT.  
9. For the Burst Read, the /UB, /LB setup time to CLK (tBC) must be satisfied. For the Burst Write, the /UB,  
/LB setup time to CLK (tBC) must be satisfied. Once /LB and /UB inputs are determined, they must not be  
changed until the end of burst operation.  
10. In case of WC = 0, /WE is HIGH.  
In case of WC = 1, /WE is LOW.  
The explanation of WC refers to Table 5-2. Mode Register Definition (5th Bus Cycle) and 5.9 /WE  
control.  
Remark H, HIGH : VIH, L, LOW : VIL, ×: VIH or VIL,  
: valid edge  
6
Preliminary Data Sheet M17507EJ2V0DS  
1...3456789...82

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