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UPD44645084F5-E37-FQ1-A PDF预览

UPD44645084F5-E37-FQ1-A

更新时间: 2024-09-13 19:49:35
品牌 Logo 应用领域
瑞萨 - RENESAS 静态存储器内存集成电路
页数 文件大小 规格书
40页 379K
描述
QDR SRAM, 8MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165

UPD44645084F5-E37-FQ1-A 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
针数:165Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.79最长访问时间:0.45 ns
最大时钟频率 (fCLK):270 MHzI/O 类型:SEPARATE
JESD-30 代码:R-PBGA-B165内存密度:67108864 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
端子数量:165字数:8388608 words
字数代码:8000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8MX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA165,11X15,40封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
电源:1.5/1.8,1.8 V认证状态:Not Qualified
最小待机电流:1.7 V子类别:SRAMs
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
Base Number Matches:1

UPD44645084F5-E37-FQ1-A 数据手册

 浏览型号UPD44645084F5-E37-FQ1-A的Datasheet PDF文件第2页浏览型号UPD44645084F5-E37-FQ1-A的Datasheet PDF文件第3页浏览型号UPD44645084F5-E37-FQ1-A的Datasheet PDF文件第4页浏览型号UPD44645084F5-E37-FQ1-A的Datasheet PDF文件第5页浏览型号UPD44645084F5-E37-FQ1-A的Datasheet PDF文件第6页浏览型号UPD44645084F5-E37-FQ1-A的Datasheet PDF文件第7页 
PRELIMINARY DATA SHEET  
MOS INTEGRATED CIRCUIT  
PD44645084, 44645094, 44645184, 44645364  
μ
72M-BIT QDRTM II SRAM  
4-WORD BURST OPERATION  
Description  
The μPD44645084 is a 8,388,608-word by 8-bit, the μPD44645094 is a 8,388,608-word by 9-bit, the μPD44645184 is a  
4,194,304-word by 18-bit and the μPD44645364 is a 2,097,152-word by 36-bit synchronous quad data rate static RAM  
fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.  
The μPD44645084, μPD44645094, μPD44645184 and μPD44645364 integrate unique synchronous peripheral  
circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive  
edge of K and K#.  
These products are suitable for application which require synchronous operation, high speed, low voltage, high density  
and wide bit configuration.  
These products are packaged in 165-pin PLASTIC BGA.  
Features  
1.8 ± 0.1 V power supply  
165-pin PLASTIC BGA (15 x 17)  
HSTL interface  
PLL circuitry for wide output data valid window and future frequency scaling  
Separate independent read and write data ports with concurrent transactions  
100% bus utilization DDR READ and WRITE operation  
Four-tick burst for reduced address frequency  
Two input clocks (K and K#) for precise DDR timing at clock rising edges only  
Two output clocks (C and C#) for precise flight time  
and clock skew matching-clock and data delivered together to receiving device  
Internally self-timed write control  
Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.  
User programmable impedance output  
Fast clock cycle time : 3.7 ns (270 MHz) , 4.0 ns (250 MHz) , 5.0 ns (200 MHz)  
Simple control logic for easy depth expansion  
JTAG boundary scan  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. M18232EJ2V0DS00 (2nd edition)  
Date Published February 2007 NS CP(N)  
Printed in Japan  
2006  
The mark <R> shows major revised points.  
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.  

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QDR SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165
UPD44645094F5-E37-FQ1-A RENESAS

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QDR SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165
UPD44645094F5-E40-FQ1-A RENESAS

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IC,SYNC SRAM,QDR,8MX9,CMOS,BGA,165PIN,PLASTIC
UPD44645094F5-E50-FQ1-A RENESAS

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