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UPD44645364F5-E40-FQ1 PDF预览

UPD44645364F5-E40-FQ1

更新时间: 2024-09-16 10:14:43
品牌 Logo 应用领域
瑞萨 - RENESAS 静态存储器
页数 文件大小 规格书
40页 379K
描述
IC,SYNC SRAM,QDR,2MX36,CMOS,BGA,165PIN,PLASTIC

UPD44645364F5-E40-FQ1 数据手册

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PRELIMINARY DATA SHEET  
MOS INTEGRATED CIRCUIT  
PD44645084, 44645094, 44645184, 44645364  
μ
72M-BIT QDRTM II SRAM  
4-WORD BURST OPERATION  
Description  
The μPD44645084 is a 8,388,608-word by 8-bit, the μPD44645094 is a 8,388,608-word by 9-bit, the μPD44645184 is a  
4,194,304-word by 18-bit and the μPD44645364 is a 2,097,152-word by 36-bit synchronous quad data rate static RAM  
fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.  
The μPD44645084, μPD44645094, μPD44645184 and μPD44645364 integrate unique synchronous peripheral  
circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive  
edge of K and K#.  
These products are suitable for application which require synchronous operation, high speed, low voltage, high density  
and wide bit configuration.  
These products are packaged in 165-pin PLASTIC BGA.  
Features  
1.8 ± 0.1 V power supply  
165-pin PLASTIC BGA (15 x 17)  
HSTL interface  
PLL circuitry for wide output data valid window and future frequency scaling  
Separate independent read and write data ports with concurrent transactions  
100% bus utilization DDR READ and WRITE operation  
Four-tick burst for reduced address frequency  
Two input clocks (K and K#) for precise DDR timing at clock rising edges only  
Two output clocks (C and C#) for precise flight time  
and clock skew matching-clock and data delivered together to receiving device  
Internally self-timed write control  
Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.  
User programmable impedance output  
Fast clock cycle time : 3.7 ns (270 MHz) , 4.0 ns (250 MHz) , 5.0 ns (200 MHz)  
Simple control logic for easy depth expansion  
JTAG boundary scan  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. M18232EJ2V0DS00 (2nd edition)  
Date Published February 2007 NS CP(N)  
Printed in Japan  
2006  
The mark <R> shows major revised points.  
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.  

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