Datasheet > UPD44645182F5-E50-FQ1

UPD44645182F5-E50-FQ1

更新时间： 2024-01-25 07:50:54

品牌	Logo	应用领域
日电电子 - NEC		静态存储器内存集成电路
页数	文件大小	规格书
40页	370K
描述
QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165

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UPD44645182F5-E50-FQ1 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.79	最长访问时间：	0.45 ns
最大时钟频率 (fCLK)：	200 MHz	I/O 类型：	SEPARATE
JESD-30 代码：	R-PBGA-B165	内存密度：	75497472 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	18
端子数量：	165	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	4MX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
最小待机电流：	1.7 V	子类别：	SRAMs
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
Base Number Matches：	1

UPD44645182F5-E50-FQ1 数据手册

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PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

PD44645082, 44645092, 44645182, 44645362

72M-BIT QDR^TMII SRAM

2-WORD BURST OPERATION

Description

The μPD44645082 is a 8,388,608-word by 8-bit, the μPD44645092 is a 8,388,608-word by 9-bit, the μPD44645182 is a

4,194,304-word by 18-bit and the μPD44645362 is a 2,097,152-word by 36-bit synchronous quad data rate static RAM

fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The μPD44645082, μPD44645092, μPD44645182 and μPD44645362 integrate unique synchronous peripheral

circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive

edge of K and K#.

These products are suitable for application which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

Features

• 1.8 ± 0.1 V power supply

• 165-pin PLASTIC BGA (15 x 17)

• HSTL interface

• PLL circuitry for wide output data valid window and future frequency scaling

• Separate independent read and write data ports with concurrent transactions

• 100% bus utilization DDR READ and WRITE operation

• Two-tick burst for low DDR transaction size

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two output clocks (C and C#) for precise flight time and clock skew matching-clock

and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.

• User programmable impedance output

• Fast clock cycle time : 4.0 ns (250 MHz), 5.0 ns (200 MHz)

• Simple control logic for easy depth expansion

• JTAG boundary scan

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M18231EJ2V0DS00 (2nd edition)

Date Published February 2007 NS CP(N)

Printed in Japan

2006

The mark <R> shows major revised points.

The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.

12 3 4 5 6 7...40

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与UPD44645182F5-E50-FQ1相关器件

型号	品牌	描述	获取价格	数据表
UPD44645182F5-E50-FQ1-A	NEC	QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165	获取价格
UPD44645184F5-E37-FQ1-A	NEC	QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165	获取价格
UPD44645184F5-E37-FQ1-A	RENESAS	QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165	获取价格
UPD44645184F5-E50-FQ1	NEC	QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165	获取价格
UPD44645184F5-E50-FQ1	RENESAS	4MX18 QDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, PLASTIC, BGA-165	获取价格
UPD44645184F5-E50-FQ1-A	NEC	QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165	获取价格

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