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UPD44645182F5-E50-FQ1

更新时间： 2024-01-23 13:56:57
品牌 Logo 应用领域
日电电子 - NEC 静态存储器内存集成电路
页数 文件大小 规格书
40页 370K
描述
QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165

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中文翻译

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UPD44645182F5-E50-FQ1 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
针数：165Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.79最长访问时间：0.45 ns
最大时钟频率 (fCLK)：200 MHzI/O 类型：SEPARATE
JESD-30 代码：R-PBGA-B165内存密度：75497472 bit
内存集成电路类型：STANDARD SRAM内存宽度：18
端子数量：165字数：4194304 words
字数代码：4000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：4MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
电源：1.5/1.8,1.8 V认证状态：Not Qualified
最小待机电流：1.7 V子类别：SRAMs
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
Base Number Matches：1

UPD44645182F5-E50-FQ1 数据手册

 浏览型号UPD44645182F5-E50-FQ1的Datasheet PDF文件第4页浏览型号UPD44645182F5-E50-FQ1的Datasheet PDF文件第5页浏览型号UPD44645182F5-E50-FQ1的Datasheet PDF文件第6页浏览型号UPD44645182F5-E50-FQ1的Datasheet PDF文件第8页浏览型号UPD44645182F5-E50-FQ1的Datasheet PDF文件第9页浏览型号UPD44645182F5-E50-FQ1的Datasheet PDF文件第10页 
μPD44645082, 44645092, 44645182, 44645362  
Pin Identification  
(1/2)  
Symbol  
Description  
A
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the  
rising edge of K for READ cycles and must meet the setup and hold times around the rising edge of K# for  
WRITE cycles. All transactions operate on a burst of two words (one clock period of bus activity). These inputs  
are ignored when device is deselected, i.e., NOP (R# = W# = HIGH).  
D0 to Dxx  
Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and K#  
during WRITE operations. See Pin Configurations for ball site location of individual signals.  
x8 device uses D0 to D7.  
x9 device uses D0 to D8.  
x18 device uses D0 to D17.  
x36 device uses D0 to D35.  
Q0 to Qxx  
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K and K# rising edges  
if C and C# are tied HIGH. Data is output in synchronization with C and C# (or K and K#), depending on the R#  
command. See Pin Configurations for ball site location of individual signals.  
x8 device uses Q0 to Q7.  
x9 device uses Q0 to Q8.  
x18 device uses Q0 to Q17.  
x36 device uses Q0 to Q35.  
R#  
Synchronous Read: When LOW this input causes the address inputs to be registered and a READ cycle to be  
initiated. This input must meet setup and hold times around the rising edge of K.  
Synchronous Write: When LOW this input causes the address inputs to be registered and a WRITE cycle to be  
initiated. This input must meet setup and hold times around the rising edge of K.  
Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble  
to be registered and written during WRITE cycles. These signals must meet setup and hold times around the  
rising edges of K and K# for each of the two rising edges comprising the WRITE cycle. See Pin  
Configurations for signal to data relationships.  
W#  
BWx#  
NWx#  
x8 device uses NW0#, NW1#.  
x9 device uses BW0#.  
x18 device uses BW0#, BW1#.  
x36 device uses BW0# to BW3#.  
See Byte Write Operation for relation between BWx#, NWx# and Dxx.  
Input Clock: A READ address and control input signal are input in synchronization with the rising edge of K and  
a WRITE address is input in synchronization with the rising edge of K#. Input data is input in synchronization  
with the rising edge of K and K#. K# is ideally 180 degrees out of phase with K. All synchronous inputs must  
meet setup and hold times around the clock rising edges.  
K, K#  
C, C#  
Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of  
C# is used as the output timing reference for first output data. The rising edge of C is used as the output  
reference for second output data. Ideally, C# is 180 degrees out of phase with C. When use of K and K# as the  
reference instead of C and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed unless C and  
C# are fixed to HIGH (i.e. toggle of C and C#).  
Preliminary Data Sheet M18231EJ2V0DS  
7
1...45678910...40

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与UPD44645182F5-E50-FQ1相关器件

型号 品牌 描述 获取价格 数据表
UPD44645182F5-E50-FQ1-A NEC QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165

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UPD44645184F5-E37-FQ1-A NEC QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165

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UPD44645184F5-E37-FQ1-A RENESAS QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165

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UPD44645184F5-E50-FQ1 NEC QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165

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UPD44645184F5-E50-FQ1 RENESAS 4MX18 QDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, PLASTIC, BGA-165

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UPD44645184F5-E50-FQ1-A NEC QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165

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